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Showing papers by "STMicroelectronics published in 1997"


Patent
01 Sep 1997
TL;DR: In this article, a multi-carrier transmission system using DMT is described, where frame synchronization is handled separately from sampling clock synchronization, although the two processes are intimately related.
Abstract: A multi-carrier transmission system using DMT It is known to recover a receiver sample and clock from a reserved carrier, a pilot carrier having a fixed phase A sampling clock oscillator in a receiver is then phase locked to the pilot carrier Multi-carrier receivers, such as DMT receivers, are normally equipped with an FFT processor A complex number representing the pilot carrier is then available from the FFT processor output If an FFT processor is not available, a one frequency DFT processor can be provided to produce a complex estimate of the pilot carrier In a DMT system, frame synchronization is handled separately from sampling clock synchronization, although the two processes are intimately related and frame synchronization must be acquired before sampling clock synchronization

302 citations


Journal ArticleDOI
06 Feb 1997
TL;DR: A simple method to solve the problem of severely degraded SNR performance in switched-capacitors by double-sampling in second-order /spl Sigma//spl Delta/ analog-to-digital converters (ADC) and the accompanying use of internal decimation to relax the bandwidth requirements of the opamps.
Abstract: An obvious way of achieving higher signal-to-noise ratio in oversampled data converters is by increasing the effective sampling rate. If all other components are kept constant, this translates into integrators with larger bandwidth that in turn results in higher overall power consumption. This work introduces the fully floating switched-capacitor configuration as a simple and robust technique to effectively double the sampling rate of oversampled data converters without compromising any aspect of the performance and yet maintaining the power levels of the conventional approach. The use of internal decimation in the switched-capacitor ladder structure of the digital-to-analog converter further helps in achieving the power budget goals. These converters have been implemented with circuitry capable of operating at a minimum supply voltage of 1.8 V under worst case process and temperature conditions and using clock bootstrapping for the transfer gates. The bootstrapping circuit described here uses a single internal capacitor and has functionality that limits the maximum clock voltage to safe levels under a wide range of supply voltages. The prototype was fabricated in a 0.5-/spl mu/m CMOS double-poly technology. The analog-to-digital converter occupies a die area of 0.11 mm/sup 2/ dissipating 550 /spl mu/W while the digital-to-analog converter occupies 0.28 mm/sup 2/ dissipating 600 /spl mu/W.

169 citations


Journal ArticleDOI
TL;DR: In this paper, the authors measured a stable leakage current at fields lower than those required for Fowler-Nordheim tunneling, which is similar to the usual stress induced leakage currents (SILC) observed after electrical stresses of MOS devices.
Abstract: MOS capacitors with a 4.4 nm thick gate oxide have been exposed to /spl gamma/ radiation from a Co/sup 60/ source. As a result, we have measured a stable leakage current at fields lower than those required for Fowler-Nordheim tunneling. This Radiation Induced Leakage Current (RILC) is similar to the usual Stress Induced Leakage Currents (SILC) observed after electrical stresses of MOS devices. We have verified that these two currents share the same dependence on the oxide field, and the RILC contribution can be normalized to an equivalent injected charge for Constant Current Stresses. We have also considered the dependence of the RILC from the cumulative radiation dose, and from the applied bias during irradiation, suggesting a correlation between RILC and the distribution of trapped holes and neutral levels in the oxide layer.

150 citations


Patent
27 Mar 1997
TL;DR: In this paper, a method and device for encoding and transmitting a clock signal, a supply voltage and bidirectional digital data from a master circuit to a slave circuit is presented.
Abstract: A method and device for encoding and transmitting a clock signal, a supply voltage and bidirectional digital data from a master circuit to a slave circuit, including the steps of: holding a first conductor at a first voltage with respect to a second conductor; periodically raising the first conductor to a second voltage with respect to the second conductor, a fixed period after a previous raising to the second voltage; holding the first conductor at the second voltage for one of a number of predetermined periods, then returning the first conductor to the first voltage, the voltage of the first conductor not falling below the first voltage; controlling the predetermined periods to each have one of a number of fixed durations, each duration having a logical significance.

128 citations


Journal ArticleDOI
TL;DR: In this article, a new driver technique that allows optimization of the switching speed, reduction of the energy losses during the switching time, and limitation of the electromagnetic interference (EMI) was proposed.
Abstract: MOSFETs and insulated gate bipolar transistor (IGBT) devices are increasingly used in electronic circuits due to both their easy driving and ability to handle high currents and voltages at high-switching frequencies. This paper deals with a new driver technique that allows optimization of the switching speed, reduction of the energy losses during the switching time, and limitation of the electromagnetic interference (EMI). First, an analysis of voltage- and current-switching waveforms of gate-insulated devices is performed. Then, a method of controlling voltage and current slopes independently is shown using the "one-cycle" method or a suitable adaptive-driving technique based on a phase-locked loop (PLL) approach. These techniques were adopted in order to allow correct generation of the gate signals regardless of the operating conditions. Finally, practical results of the proposed driving circuit obtained using a single IGBT switch chopper are presented.

100 citations


Patent
17 Nov 1997
TL;DR: An integrated circuit package for direct mounting of an integrated circuit die to a printed circuit board is disclosed in this paper, which includes a silicon sensor that detects changes in external variables, such as providing an image of a human fingerprint.
Abstract: An integrated circuit package for direct mounting of an integrated circuit die to a printed circuit board is disclosed. The integrated circuit die includes a silicon sensor that detects changes in external variables, such as providing an image of a human fingerprint. The integrated circuit die has wire bond pads formed along only one side thereof to provide maximum exposure of the top surface area of the silicon sensor. The die is affixed to the printed circuit board and an adhesive surface coating, such as epoxy, is applied to the die and the printed circuit board for sealing the die thereto. The adhesive surface coating is formed from a first bead applied to the printed circuit board to cover at least the ends of the wires bonded to the board and a second bead applied to the first bead and the die to enclose the sides of the die and partially overlap the wire band pads and wires on top surface thereof.

96 citations


Journal ArticleDOI
TL;DR: In this paper, an innovative method to control carrier lifetime locally and efficiently in Insulated Gate Bipolar Transistors (IGBTs) is presented based on the formation of void layers by low-energy and high-dose He implants and annealing.
Abstract: An innovative method to control carrier lifetime locally and efficiently in Insulated Gate Bipolar Transistors (IGBTs) is presented. It is based on the formation of void layers by low-energy and high-dose He implants and annealing. Voids introduce two well-defined midgap trap levels in silicon. HFIELDS simulations demonstrate the increase of surface hole concentration when a well localized recombination region is introduced in the buffer layer. High-speed IGBTs were fabricated both with voids in the buffer layer or with unlocalized recombination centres. Devices with localized bandgap centres show a lower on-resistance with a fast turn-off behavior.

89 citations


Journal ArticleDOI
01 Mar 1997
TL;DR: An extensive survey of trends in embedded processor use with an emphasis on emerging applications in wireless communication, multimedia, and general telecommunications and the importance of application-specific instruction-set processors (ASIPs) in high-volume, low cost applications is presented.
Abstract: We present an extensive survey of trends in embedded processor use with an emphasis on emerging applications in wireless communication, multimedia, and general telecommunications. We demonstrate the importance of application-specific instruction-set processors (ASIPs) in high-volume, low cost applications. We also examine some of the underlying trends of the applications in which embedded processors are used. This is followed by a description of embedded software development tool requirements. High-performance software compilation emerges as a key requirement. Finally, specific industrial case studies of products in MPEG, videophone, and low-cost digital signal processor (DSP) applications are used to illustrate the architecture design tradeoffs, and highlight specific tool requirements. A companion paper (Goosens et al., 1997) presents a comprehensive survey of embedded software development tools, focusing mostly on retargetable software compilation.

89 citations


Journal ArticleDOI
TL;DR: The authors determine the necessary conditions for fault secureness and derive designs embodying these conditions that are compatible with systems checked by parity codes.
Abstract: Although parity prediction arithmetic operators are compatible with systems checked by parity codes, they are not secure against single faults. The authors determine the necessary conditions for fault secureness and derive designs embodying these conditions.

83 citations


Patent
22 Aug 1997
TL;DR: In this article, an electronic system coupled to a memory, comprising of a core logic chipset having access to the memory, a decoder having access access to memory, and a memory interface coupled to the decoder, is presented.
Abstract: An electronic system coupled to a memory, comprising: a core logic chipset having access to the memory; a decoder having access to the memory; a memory interface coupled to the core logic chipset and the decoder, the memory interface having an arbiter coupled to a core logic chipset direct memory access engine and a decoder direct memory access engine, the arbiter for selectively providing access for the core logic chipset and the decoder to the memory; and a bus coupled to the memory, the first device and the decoder, wherein the decoder and the core logic chipset are coupled to the memory through the bus, the bus having a bandwidth providing access to the memory sufficient to maintain real-time operation of the decoder and to allow the core logic chipset to access the memory thereby enabling the decoder and the core logic chipset to share the memory; wherein said memory interface is operable to provide memory access to the core logic chipset through said bus when the decoder is not operating.

77 citations


Journal ArticleDOI
01 Mar 1997
TL;DR: This paper discusses design technology issues for embedded systems using processor cores, with a focus on software compilation tools, and conducts a comprehensive survey of both existing and new software compilation techniques that are considered important in the context of embedded processors.
Abstract: The increasing use of embedded software, often implemented on a core processor in a single-chip system, is a clear trend in the telecommunications, multimedia, and consumer electronics industries. A companion paper (Paulin et al., 1997) presents a survey of application and architecture trends for embedded systems in these growth markets. However, the lack of suitable design technology remains a significant obstacle in the development of such systems. One of the key requirements is more efficient software compilation technology. Especially in the case of fixed-point digital signal processor (DSP) cores, it is often cited that commercially available compilers are unable to take full advantage of the architectural features of the processor. Moreover, due to the shorter lifetimes and the architectural specialization of many processor cores, processor designers are often compelled to neglect the issue of compiler support. This situation has resulted in an increased research activity in the area of design tool support for embedded processors. This paper discusses design technology issues for embedded systems using processor cores, with a focus on software compilation tools. Architectural characteristics of contemporary processor cores are reviewed and tool requirements are formulated. This is followed by a comprehensive survey of both existing and new software compilation techniques that are considered important in the context of embedded processors.

Patent
26 Sep 1997
TL;DR: In this paper, a method and apparatus for decoding a multi-channel audio bitstream in which adaptive frequency domain downmixer is used to downmix, according to long and shorter transform block length information, is presented.
Abstract: A method and apparatus for decoding a multi-channel audio bitstream in which adaptive frequency domain downmixer is used to downmix, according to long and shorter transform block length information, the decoded frequency coefficients of the multi-channel audio such that the long and shorter transform block information is maintained separately within the mixed down left and right channels. In this way, the long and shorter transform block coefficients of the mixed down left and right channels can be inverse transformed adaptively according to the long and shorter transform block information, and the results of the inverse transform of the long and short block of each of the left and right channel added together to form the total mixed down output of the left and right channel.

Patent
01 Sep 1997
TL;DR: In this paper, it is known that a receiver can recover a receiver sampling clock from a reserved carrier, a pilot carrier, having a fixed phase, by phase-locking a sampling clock oscillator in a receiver.
Abstract: In multi-carrier transmission systems using, for example, DMT, it is known to recover a receiver sampling clock from a reserved carrier, a pilot carrier, having a fixed phase. A sampling clock oscillator in a receiver is then phase-locked to the pilot carrier. Multi-carrier receivers, such as DMT receivers, are normally equipped with a FFT processor. A complex number representing the pilot carrier is then available from the FFT processor output. If a FFT processor is not available, a one-frequency DFT processor can be provided to produce a complex estimate of the pilot carrier. In a DMT system, frame synchronisation is handled separately from sampling clock synchronisation, although the two processes are intimately related and frame synchronisation must be acquired before sampling clock synchronisation.

Patent
Livio Baldi1
23 Sep 1997
TL;DR: A currency note includes an identification and/or authentication element including an integrated circuit as mentioned in this paper, which can store, securely in electronic form and accessible from outside, such information as: the value, serial number, issuer, and date of issuance.
Abstract: A currency note includes an identification and/or authentication element including an integrated circuit. The integrated circuit can store, securely in electronic form and accessible from outside, such information as: the value, serial number, issuer, and date of issuance.

Patent
03 Jun 1997
TL;DR: In this paper, an improved sensing device for an integrated circuit memory device is provided, in which memory cells are formed by insulated gate transistors, such as EPROMs and flash EPRO.
Abstract: An improved sensing device for an integrated circuit memory device is provided. In particular, the memories can be those in which memory cells are formed by insulated gate transistors, such as EPROMs and flash EPROMs. Conventionally, such memories use static sence amplifiers. The present invention provides a dynamic sence amplifier suitable for use in these memories.

Journal ArticleDOI
TL;DR: In this paper, the elastic properties of dielectric silicate glass films have been studied by means of the Brillouin light scattering technique and the phase velocity of both the surface Rayleigh wave and the longitudinal wave in the film material have been measured and the two independent elastic constants c 11 and c 44 evaluated.

Patent
09 Apr 1997
TL;DR: In this article, a transition time from one step to the next is determined by detecting a zero crossing of a back emf in one of the plurality of windings in a brushless motor.
Abstract: A method and apparatus for controlling a brushless motor having a plurality of windings switched through a sequence of steps includes determining a transition time from one step to the next. The transition time is determined by detecting a zero crossing of a back emf in one of the plurality of windings. A delayed time to be added to the transition time is determined wherein the delayed time is selected according to the step in the sequence of steps being executed and is dependent on the duration of one of a preceding interval between zero crossings. A delay time proportional to a duration of a last shortest interval is supplied to follow a longest interval. A delay time proportional to a duration of a last longest interval is supplied to follow a shortest interval and a delay time proportional to a duration of a medium interval is supplied to follow a medium interval. The method may be used, for example, with a star or delta connected motor having any number of windings.

Patent
27 Feb 1997
TL;DR: In this paper, the shape of the resulting PWM driving signal will include additional PWM pulses during the transitioning period that provide for a trapezoidal shaping of the current supplied to each of the phase coils in the motor.
Abstract: Methods and apparatuses are provided for use in driving a multiple-phase brushless motor. The methods and apparatuses include generating a slewed phase control signal for each phase of the motor. The slewed phase control signals are substantially proportional to a speed control signal during non-transitioning periods, and are slewed from one state to the next state over time during transitioning periods. The transitioning periods being associated with a commutation point. The slewed phase control signals are used to generate pulse width modulated (PWM) driving signals, for each phase of the motor. Thus, the shape of the resulting PWM driving signal will include additional PWM pulses during the transitioning period that provide for a trapezoidal shaping of the current supplied to each of the phase coils in the motor. The result is that torque ripple is reduced because the overall current applied to the motor and the torque resulting therefrom will tend to be more constant during commutation.

Patent
28 Feb 1997
TL;DR: In this article, a voltage regulator with load pole stabilization is disclosed, where a variable impedance device such as a FET transistor configured as a variable resistor is connected between the input and output of the gain stage to provide variable zero to cancel the varying pole when the output current drawn by the load fluctuates.
Abstract: A voltage regulator with load pole stabilization is disclosed. An error amplifier has a non-inverting input receiving a reference voltage and an inverting input receiving a feedback voltage from the output of the voltage regulator. A gain stage has an input connected to the output of the error amplifier and an output connected to a pass transistor that provides current to a load. A variable impedance device such as a FET transistor configured as a variable resistor is connected between the input and output of the gain stage to provide variable zero to cancel the varying pole when the output current drawn by the load fluctuates. Consequently, the disclosed voltage regulator has high stability without a significant increase in power dissipation.

Patent
11 Aug 1997
TL;DR: In this article, the average value of the current in an inductive load driven through a bridge power stage in a PWM mode is monitored by sampling at a half way point of an active driving phase and at the half-way point of a current recirculation phase by closing the switch with a synchronizing pulse that coincides with the half way points of these phases of operation.
Abstract: Monitoring of current flowing through an inductive load driven through a bridge power stage in a PWM mode, comprises sampling the signal output by a sensing amplifier with a Sample & Hold circuit including a sampling switch and a storing capacitor The average value of the current in the load is monitored by sampling at a half way point of an active driving phase and at a half way point of a current recirculation phase by closing the switch with a synchronizing pulse that coincides with the half way points of these phases of operation The monitoring uses a pair of complementary periodic reference signals and uses a sensing amplifier to amplify the signal existing on a current sensing resistor functionally connected in series with the load This produces an amplified signal representative of the current in the load to be fed to an input of an error amplifier driving a power amplifier of the bridge stage The synchronizing pulse is generated in coincidence with the peak and with the virtual zero crossing of the two reference periodic signals, out of phase from one another by 180 degrees A two-input logic AND gate, combining the synchronizing pulse and a masking signal of a preestablished duration generated at every switching of the bridge stage may also be employed

Patent
18 Jun 1997
TL;DR: In this article, the current flowing through a cell to be read, forming part of a nonvolatile memory array and presenting a characteristic with a predetermined slope, is amplified N times and compared with a reference current presenting a two-part characteristic: a first portion extending between a predetermined threshold value and a trigger value, and a second portion extending from the trigger value.
Abstract: The current flowing through a cell to be read, forming part of a nonvolatile memory array and presenting a characteristic with a predetermined slope, is amplified N times and compared with a reference current presenting a two portion characteristic: a first portion extending between a predetermined threshold value and a trigger value, and presenting a slope equal to that of the memory cell characteristic, and a second portion extending from the trigger value, and presenting a slope amplified N times with respect to that of the cell characteristic and therefore equal to the amplified slope of the cell.

Patent
Robert Warren1
20 Oct 1997
TL;DR: In this article, a test access port controller for effecting communications across a chip boundary having a test mode and a diagnostic mode of operation, wherein in the test data is resultant data from a test operation having an expected and time delayed relationship, and in the diagnostic data is conveyed both on and off chip in the form of respective independent input and output serial bit streams simultaneously through the test access controller.
Abstract: There is disclosed a test access port controller for effecting communications across a chip boundary having a test mode and a diagnostic mode of operation, wherein in the test mode of operation the test data is resultant data from a test operation having an expected and time delayed relationship, and in the diagnostic mode of operation diagnostic data is conveyed both on and off chip in the form of respective independent input and output serial bit streams simultaneously through the test access port controller.

Patent
29 Aug 1997
TL;DR: An ATM routing switch for bidirectional transmission of at least two types of cell (61), one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity (160) for cells of the first type, a second reserve buffer (150) for cell of the second type and control circuitry (39, 40, 41) for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity(160) is reached by input of cells of said first type and discarding input cells of such cells
Abstract: An ATM routing switch for bidirectional transmission of at least two types of cell (61), one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity (160) for cells of the first type, a second reserve buffer capacity (150) for cells of said second type and control circuitry (39, 40, 41) for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity (160) is reached by input of cells of said first type, and discarding input cells of said second type if a predetermined threshold for said second buffer capacity (150) has been reached by input of cells of said second type.

Patent
08 Oct 1997
TL;DR: In this paper, a charge pump comprises a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal providing an output voltage higher than the voltage supply.
Abstract: A charge pump comprises a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal of the charge pump providing an output voltage higher than the voltage supply. Each stage comprises unidirectional current flow MOS transistor means connected between a stage input terminal and a stage output terminal allowing current to flow only from said stage input terminal to said stage output terminal, and a first capacitor with one plate connected to said stage output terminal and another plate driven by a respective first digital signal periodically switching between ground and said voltage supply. The unidirectional current flow MOS transistor means of the stages have independent bulk electrodes, and a bias voltage generator circuit is provided for biasing the bulk electrodes of said unidirectional current flow MOS transistor means at respective bulk potentials which become progressively higher going from the stages proximate to said input terminal to the stages proximate to said output terminal of the charge pump.

Patent
David Wong1
29 Dec 1997
TL;DR: In this paper, a system and method for adding another floating point register set in the floating point execution unit of a microprocessor is described. Butler et al. proposed a method that allows for either of the two register sets (or a combination thereof) to be, at a given point in time, the working set, with the other being a shadow register set.
Abstract: A system and method is provided that adds another floating point register set in the floating point execution unit of a microprocessor. Thus, when the floating point state, or environment is stored as an image into memory, it is also stored as a copy in the additional internal registers. When the state, or environment, is to be restored the necessary information (data and/or instructions) is normally present in the additional registers, thus saving CPU cycles by avoiding reloading the image from memory. The present invention allows for either of the two register sets (or a combination thereof) to be, at a given point in time, the working set, with the other being a shadow register set. All of the memory write cycles are monitored (snooped) to determine if the information in the on-chip image has been altered, since the last store operation. The shadowed register file will allow the state of the floating point register file to be kept "as is" on the occurrence of a task switch.

Patent
Robert Warren1
19 Dec 1997
TL;DR: In this article, a single chip integrated circuit device includes a breakpoint range unit having first and second breakpoint registers for holding respectively lower and upper breakpoint addresses between which normal operation of the CPU is to be interrupted for diagnostic purposes.
Abstract: A single chip integrated circuit device includes a breakpoint range unit having first and second breakpoint registers for holding respectively lower and upper breakpoint addresses between which normal operation of the CPU is to be interrupted for diagnostic purposes. The breakpoint range unit further has comparison logic operative to compare the contents of the address register with each of a lower and upper breakpoint address, and to issue a breakpoint signal when the address held in an address register is equal to the lower breakpoint address or between the lower and upper breakup addresses. On chip control logic is connected to receive the breakpoint signal and arranged to interrupt normal operation of the CPU when the breakpoint signal is received. The comparison logic includes inverse state logic configured to set an inverse state indicator to cause generation of the breakpoint signal outside the address range defined by the upper and lower breakpoint address.

Patent
29 Aug 1997
TL;DR: In this article, a linear type of voltage regulator, having an input terminal adapted to receive a supply voltage thereon, and an output terminal adapting to deliver a regulated output voltage, includes a power transistor and a driving circuit therefor.
Abstract: A linear type of voltage regulator, having an input terminal adapted to receive a supply voltage thereon, and an output terminal adapted to deliver a regulated output voltage, includes a power transistor and a driving circuit therefor. The driving circuit includes an operational amplifier having a differential input stage biased by a bias current which varies proportionally with the output current of the regulator.

Patent
Robert Warren1
29 Oct 1997
TL;DR: In this article, the serial to parallel data packet converter is used to convert serial data packets into parallel data for supply in a forward direction to the bus system, such that if the serial data packet has a length which exceeds the bus width, the data packet is converted into successive sets of parallel data and placed sequentially on the bus.
Abstract: A single chip integrated circuit device includes a bus system for effecting communication of parallel data on chip, functional circuitry connected to the bus system for executing an operation in response to parallel data received from the bus system, an external port, and a serial to parallel data packet converter interconnecting the parallel bus system and the external port. The external port includes a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device. The serial data packets each include a packet identifier indicating the length of the data packet and information defining an operation to be executed by the functional circuitry. The serial to parallel data packet converter is operable to read the packet identifier to determine the length of serial packets which are input through the port and to convert them into parallel data for supply in a forward direction to the bus system, such that if the serial data packet has a length which exceeds the bus width, the serial data packet is converted into successive sets of parallel data and placed sequentially on the bus system. The serial to parallel converter further includes flow control logic for indicating that it is ready to receive a subsequent data packet by transmitting a flow control signal in the reverse direction, and for requesting access to the bus system when the parallel data is ready to be output to the functional circuitry. In this device, the serial to parallel conversion of the serial packets into parallel data is effected without involving the functional circuitry, and the parallel data causes the functional circuitry to execute an operation dependent on the information contained in the serial packets from which it has been converted.

Patent
25 Nov 1997
TL;DR: In this paper, a method of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed, where an opening is formed partially through an insulating layer overlying a conductive region.
Abstract: A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening. According to a further alternate embodiment, an etch stop layer is formed between the insulating layer and conductive region and an opening is formed in the insulating layer exposing the etch stop layer. A sidewall spacer film is formed over the insulating layer and the etch stop layer, both layers having a similar etch rate for a given etchant. The etch stop and spacer layers are etched in the opening to expose the underlying conductive layer thereby forming a contiguous sidewall spacer and etch stop layer on the sides of and under the insulating layer, thereby decreasing the contact dimension of the opening.

Patent
23 Jul 1997
TL;DR: In this paper, the authors proposed a tunable add/drop optical device for injecting or extracting (add/drop) at least a selected optical channel or carrier wavelength in or from a set of multiplexed channels or carriers of different wavelengths comprising a plurality of directional couplers (AD1... AD6) and a plurality OF phase-shift stages (SF1...SF5) alternately connected in cascade, wherein each phase-shifted stage defines a certain optical path length difference (ΔL1... ΔL5) between two distinct optical paths of the stage.
Abstract: Tunable add/drop optical device for injecting or extracting (add/drop) at least a selected optical channel or carrier wavelength in or from a set of multiplexed channels or carriers of different wavelengths comprising a plurality of directional couplers (AD1... AD6) and a plurality of phase-shift stages (SF1...SF5) alternately connected in cascade, wherein each phase-shift stage defines a certain optical path length difference (ΔL1... ΔL5) between two distinct optical paths of the stage. The tuning is performed modifying the refraction index of one path of said phase shift stages by means of Joule effect heating strips (L1... L5) or by means of metallic field plates adapted to receive a signal suitable to modify the electric field intensity. The first two phase-shift stages of said plurality of phase-shift stages have differences of length of optical paths different from each other and in a preestablished ratio while the remaining phase-shift stages have differences of length of optical paths identical. It is thus possible to provide a device having an exceptionally flat cross response characteristic, substantially free of ripple due to an inevitable truncation of the Fourier expansion series.