Showing papers by "STMicroelectronics published in 1998"

New insights in the relation between electron trap generation and the statistical properties of oxide breakdown

Abstract: In this paper it is demonstrated in a wide stress field range that breakdown in thin oxide layers occurs as soon as a critical density of neutral electron traps in the oxide is reached. It is proven that this corresponds to a critical hole fluence, since a unique relationship between electron trap generation and hole fluence is found independent of stress field and oxide thickness. In this way literature models relating breakdown to hole fluence or to trap generation are linked. A new model for intrinsic breakdown, based on a percolation concept, is proposed. It is shown that this model can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the Q/sub BD/-distribution for ultrathin oxides. An important consequence of this large spread is the strong area dependence of the Q/sub BD/ for ultrathin oxides.

Capacitive distance sensor

Abstract: A distance sensor has a capacitive element in turn having a first capacitor plate which is positioned facing a second capacitor plate whose distance is to be measured. In the case of fingerprinting, the second capacitor plate is defined directly by the skin surface of the finger being printed. The sensor comprises an inverting amplifier, between the input and output of which the capacitive element is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Run-length encoding

Abstract: A method for run-length encoding two or more data values, the method comprising: loading the data values into storage by forming a first data string, the data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values; generating a second data string having a data sub-string corresponding to each data sub-string of the first data string, all the bits of each of the data sub-strings of the second data string having a first predetermined value if all the bits of the corresponding data sub-string of the first data string have a second predetermined value and having a third predetermined value if any of the bits of the corresponding data sub-string of the first data string has other than the second predetermined value; starting from a predetermined end of the second data string, counting the number of consecutive bits of the second data spring having the first predetermined value; and dividing the said number by the number of bits in each data sub-string.

Radiation induced leakage current and stress induced leakage current in ultra-thin gate oxides

Abstract: Low-field leakage current has been measured in thin oxides after exposure to ionising radiation. This Radiation Induced Leakage Current (RILC) can be described as an inelastic tunnelling process mediated by neutral traps in the oxide, with an energy loss of about 1 eV. The neutral trap distribution is influenced by the oxide field applied during irradiation, thus indicating that the precursors of the neutral defects are charged, likely to be defects associated with trapped holes. The maximum leakage current is found under zero-field condition during irradiation, and it rapidly decreases as the field is enhanced, due to a displacement of the defect distribution across the oxide towards the cathodic interface. The RILC kinetics are linear with the cumulative dose, in contrast with the power law found on electrically stressed devices.

Spectrum folding and phase noise in LC tuned oscillators

Abstract: We present a theory of the noise transfer in LC tuned oscillators accounting for the nonlinear operation of the transconductor. We show that the transconductor switching causes a folding of the wide-band noise such as the thermal noise of the spreading resistance of the bipolar transistors and the noise of the tail current generator. The effect is similar to what happens in sampled systems, however, for a careful evaluation of the oscillator phase noise, the correlations between the folded terms is of chief importance. We show how to account for the effect, we assess the impact on the oscillator noise performance and we give the guidelines for the circuit optimization.

Process for forming front-back through contacts in micro-integrated electronic devices

Abstract: The process comprises the steps of: forming a through hole from the back of a semiconductor material body; forming a hole insulating layer of electrically isolating material laterally covering the walls of the through hole; forming a through contact region of conductive material laterally covering the hole insulating layer inside the hole and having at least one portion extending on top of the lower surface of the body; forming a protective layer covering the through contact region; and forming a connection structure extending on top of the upper surface of the body between and in electrical contact with the through contact region and the electronic component.

Transformer for integrated circuits

Abstract: A invention provides a transformer for use in integrated circuits, comprising four layers of conductive lines, separated from each other by first, second and third insulating layers. First conductive vias traverse the second insulating layer to connect said second and third pluralities of conducting lines, to form a first winding. Second conductive vias traverse the first, second and third insulating layers to connect said first and fourth pluralities of conducting lines to form a second winding, about and approximately concentric with said first winding.

One-pass variable bit rate moving pictures encoding

Abstract: A method and apparatus for encoding digital video utilising a single pass variable bit rate encoding procedure. An encoding quality is set and the bit rate for encoding blocks or frames in the sequence of moving pictures is determined to achieve the selected quality according to the complexity of the video sequence. The bit rate is constrained by predetermined upper and lower bit rate limits.

A cache system for concurrent processes

Abstract: A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

Solid state fingerprint sensor packaging apparatus and method

Abstract: A planar, capacitive-type, rectangular, and multi-pixel fingerprint sensing array is mounted on the horizontal and generally rectangular top-surface of a dome that extends upward generally from the center of a horizontally disposed and generally rectangular silicon substrate member. The dome is formed by four upward extending and inclined, or tapered, side wall surfaces, at least one wall surface of which carries electrical circuit paths that electrically connected to the various circuit elements of the sensing array. A generally rectangular, encircling and wall-like card carrier assembly includes a generally horizontal upper-surface having a generally centered opening through which only the dome and sensing array project upward. The bottom-surface of the card carrier assembly is mounted to edge portions of the silicon substrate member in a manner to surround and protect all but the upward extending dome. A flexible membrane or laminate is sealed to the top-surface of the card carrier assembly to form a flexible surface over the sensing array. The card carrier assembly includes a circuit path having an external portion and having an internal portion that connects to the wall-mounted internal electrical circuit paths, the external portion providing external connection to the internal sensing array.

Low power RAM memory cell using a precharge line pulse during write operation

Abstract: A semiconductor memory cell that includes a word line, two bit lines, a precharge line, and two cross-coupled inverters. Each of the inverters is formed by a P-channel transistor and an N-channel transistor. Additionally, a first access transistor selectively couples one bit line to the output of one inverter, and a second access transistor selectively couples the other bit line to the output of the other inverter. One terminal of the N-channel transistor of each of the inverters is connected to the precharge line. In a preferred embodiment, the access transistors are P-channel transistors and the gate terminal of each PMOS access transistor is connected to the word line. Additionally, the present invention provides a method of writing data to a semiconductor memory cell that is connected to a pair of bit lines.

Solid state capacitive switch

Abstract: A fingertip-operated solid state capacitance switch detects a capacity change that is induced by the physical contact of an ungrounded fingertip to an external dielectric surface of the solid state switch. The input and output of a solid state signal-inverting amplifier are respectively connected to two relatively large and ungrounded capacitor plates that are associated with, but electrically isolated from, the switch's external dielectric surface. An ungrounded fingertip forms a third capacitor plate on the switch's external surface. The solid state amplifier detects the presence of a fingertip on the switch's external surface by way of a change in capacitance within a compound, three plate, capacitor that includes the two ungrounded capacitor plates and the ungrounded fingertip that is resident on the switch's external surface. An automatic gain control circuit is provided to adjust the value of an amplifier reference voltage when the solid state switch is not operating, thereby allowing the solid state switch to adapt to changeable ambient conditions. A momentary switch and a toggle flip-flop latched switch are provided. A linear switch array having a movable control knob and a linear LED indicator array is provided. The momentary solid state switch is constructed to operate as a temporal code detector that detects a coded sequence of switch-taps and a coded time interval between adjacent switch-taps.

Recent developments in high integration multi-standard CMOS transceivers for personal communication systems

Abstract: Issues associated with the integration of transceiver components on to a single silicon substrate are discussed. In particular, recently proposed receiver and transmitter architectures for high integration are examined on the promise of providing multistandard capability. In addition, existing barriers to lower power transceiver operation are examined as well as some proposed directions for future integrated transceiver research and development.

Transaction interface for a data communication system

Abstract: A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from or sent to a 1394 bus. A kernel/scheduler/dispatcher is used to allocate memory resources, and start a variety of tasks and services. The tasks and services vary depending on protocols used in a transport layer and application layer used in conjunction with the 1394 layers. Each task operates according to a state machine progression. The transaction interface accepts data information from the tasks and forms data packets for delivery to the 1394 bus. The data packets are initially sent via an associated hardware register, but if busy, the transaction interface polls for other available registers. In addition, all queued transactions are loaded into registers in the most expedient manner.

NMOS negative charge pump

Abstract: A negative charge pump circuit comprises a plurality of charge pump stages connected in series to each other. Each stage has a stage input terminal and a stage output terminal. A first stage has the stage input terminal connected to a reference voltage, a final stage has the stage output terminal operatively connected to an output terminal of the charge pump at which a negative voltage is developed; intermediate stages have the respective stage input terminal connected to the stage output terminal of a preceding stage and the respective stage output terminal connected to the stage input terminal of a following stage. Each stage comprises a first N-channel MOSFET with a first electrode connected to the stage input terminal and a second electrode connected to the stage output terminal, a second N-channel MOSFET with a first electrode connected to the stage output terminal and a second electrode connected to a gate electrode of the first N-channel MOSFET, a boost capacitor with one terminal connected to the gate electrode of the first N-channel MOSFET and a second terminal driven by a respective first digital signal switching between the reference voltage and a positive voltage supply, and a second capacitor with one terminal connected to the charge pump stage output terminal and a second terminal connected to a respective second digital signal switching between the reference voltage and the voltage supply. A gate electrode of the second N-channel MOSFET is connected, in the first stage, to a third digital signal switching between the reference voltage and the voltage supply, while in the remaining stage the gate electrode of the second N-channel MOSFET is connected to the stage input terminal.

Low-cost semiconductor user input device

Abstract: A low-cost semiconductor user input device for controlling the position of a pointer on a display includes a small array of composite sensors. Each composite sensor of the array is adapted to detect movement of a fingerprint feature. The user input device moves the pointer based upon the net movement detected by the composite sensors of the array.

Multiple transistor dynamic random access memory array architecture with simultaneous refresh of multiple memory cells during a read operation

Abstract: A four transistor dynamic memory cell architecture and refresh technique which allows for cell refresh to occur during a read operation. The access and memory transistors of the individual memory cells are fabricated with a relative width-to-length ratio such that it is sufficient to merely activate the associated word line to perform the refresh operation. This is accomplished without activating the read sense amplifier resulting in lower power consumption and the retention of most recently read data. Multiple word lines may be activated concurrently utilizing the technique disclosed to further reduce the refresh rate overhead in a memory array and increase the overall memory array bandwidth.

Pixel correction system and method for CMOS imagers

Abstract: Disclosed is a fault tolerant CMOS image sensor that includes circuitry for identifying defective pixels and masking them during image generation. Masking may involve, in one example, replacing the output of a given pixel with an average of the output of surrounding non-faulty pixels. Thus, while image sensors may be fabricated with some number of faulty pixels, the images produced by such sensors will not have undesirable bright or dark spots. The disclosed sensor includes (a) one or more pixels (active or passive) capable of providing outputs indicative of a quantity of radiation to which each of the one or more pixels has been exposed; and (b) one or more circuit elements electrically coupled to the one or more pixels and configured to identify and correct faulty pixels in the CMOS imager. The one more pixels each include a photodiode diffusion formed in a well and a tap to power or ground also formed in the well. The disclosed sensor also identifies pixels that were initially acceptable but later became defective. The newly defective pixels so identified may then be masked to thereby increase the CMOS detector lifetime.

A /spl plusmn/30% tuning range varactor compatible with future scaled technologies

Abstract: A /spl plusmn/30% capacitance modulation of a new variable capacitor has been achieved for a 2 V variation in the controlling bias voltage. The realized varactor is based on a polysilicon/oxide/n-well structure, implemented in a 0.35 /spl mu/m standard CMOS process. The quality factor for a 3.1 pF sample ranges from 17 to 33, at 1800 MHz.

Bus interface unit having dual purpose transaction buffer

Abstract: A bus interface unit includes a random-access transaction buffer and at least one pointer queue. The transaction buffer stores entries for both in-order transactions and combinable write transactions, and the pointer queue stores pointers to the buffer entries for in-order transactions so as to order the in-order transactions. When a received combinable write transaction has a writing address that falls within the address range of a stored combinable write transactions, the received transaction is merged with the stored transaction. Additionally, a method is provided for processing requested bus transactions. The bus interface unit determines if a requested transaction is a combinable write transaction. If not, address and data information for the requested transaction is loaded into an empty entry in a random-access buffer, and a pointer to that buffer entry is placed in a pointer queue. Alternatively, if the requested transaction is a combinable write transaction, the bus interface unit determines if the transaction's write address falls within the address range of a stored combinable write transaction. If so, the requested transaction is merged with the stored transaction. In a preferred embodiment, if the write address does not fall within the address range of any stored combinable write transaction, the data information for the requested transaction is loaded into an empty entry in the random-access buffer.

Isolation between power supplies of an analog-digital circuit

Abstract: The present invention relates to a composite integrated circuit including at least one well that separates analog and digital blocks of the circuit, this well being connected to a first terminal of a power supply of biasing of one of the two blocks, and being of type opposite to that of the circuit substrate, and a resistor being interposed on the well biasing link.

Network device and method of controlling flow of data arranged in frames in a data-based network

Abstract: A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.

Pipelined non-blocking level two cache system with inherent transaction collision-avoidance

Abstract: A cache subsystem in a data processing system is structured to place the L1 cache RAMs after the L2 cache RAMs in the pipeline for processing both CPU write transactions and L1 line-fill transactions. In this manner the lines loaded into the L1 cache are updated by all CPU write transactions without having to perform any explicit checks. The present invention also places the L1 tag RAM before the L1 data RAM for both CPU write transactions and L1 line-fill transactions, such that CPU write transactions may check that a line is in the L1 cache before updating it. L1 line-fill transactions can then check that the line to be transferred from the L2 cache to the L1 cache is not already in the L1 cache.

Process for manufacturing semiconductor packages comprising an integrated circuit

Abstract: A process for manufacturing semiconductor packages comprising, respectively, a substrate, a chip which forms an integrated circuit and is attached to one region of the substrate, electrical connection means connecting the chip to a group of external electrical connection regions lying on one face of the substrate, as well as an encapsulation encasement. The process consists in producing, in a matrix configuration, a multiplicity of groups of connection regions (104a) on a common substrate plate (102), corresponding to as many chip attachment regions (109), in attaching a chip (103) to each attachment region (109) of the common substrate plate, in electrically connecting each chip (103) to the associated electrical connection regions (104a), so as to obtain an assembly (111) consisting of the substrate plate and the connected chips. The process consists, in a second step, in placing this assembly (111) in a mold (112) and in injecting an encasement material (106) into the mold so as to obtain, in a single molding operation, a parallelepipedal block (117) and then, in a subsequent step, in cutting the said parallelepipedal block (117) through its thickness into units, each constituting a semiconductor package.

Method and network device for creating circular queue structures in shared memory

Abstract: A method and device of creating one or more buffer structures in a shared memory that exists between a host and a network device is disclosed. The method includes the step of storing within a block of shared memory an administration block having a base address and a descriptor ring parameter, which includes information relating to a descriptor ring and frame data buffer sizes. The base address of the administration block is written into the network device. An initialization command is then issued from the host to the network device. The network device reads the administration block and shared memory and one or more descriptors are constructed within the network device. Each descriptor points to a frame data buffer within shared memory. The descriptors are then stored.

Method and circuit for determining the velocity of a data detector mechanism of a mass storage device, or the like, using a BEMF voltage in the associated voice coil

Abstract: A circuit and method for measuring a back EMF voltage of a voice coil in a mass storage device, or the like, includes an amplifier connected across the coil to produce an output signal proportional to a voltage across the coil and a circuit connected to selectively connect the output signal of the amplifier to a circuit output when a driving current is not applied to said coil. A sample window is generated after drive currents within the coil have been allowed to decay to zero, and between a time during which a PWM signal changes from negative to positive and a time when the PWM waveform crosses a voltage error value.

Detection of instantaneous position of the rotor of a brushless DC motor driven in a tripolar mode

Abstract: The sensing of the rotor position for synchronizing the drive of a multiphase brushless motor when driven in a "multipolar" mode is carried out by interrupting the driving current in at least one of the windings of the motor coupled with a zero-cross sensing circuit of the BEMF signal (BEMF DETECT CIRCUIT), by means of a first logic signal (ENABLE), enabling a logic gate (AND) for asserting a zero-cross event detected by the circuit, by a second logic signal (MASK) and simultaneously resetting the first (ENABLE) and second (MASK) signals after a certain period of time from the instant of interruption.

Remanent memory device

Abstract: A remanent, electrically programmable and erasable, memory device comprises of a MOS type transistor whose gate insulator contains charged mobile species is disclosed. The gate insulator is comprised transversely of a sandwich comprising at least five areas. Two intermediate areas have first band-gap values, and two endmost and a central areas have band gap values greater than the first values.

Voltage regulator for single feed voltage memory circuits, and flash type memory in particular

Abstract: A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.

FLASH-EPROM with embedded EEPROM

Abstract: Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low power consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells, as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.