Showing papers by "STMicroelectronics published in 2001"

A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers

Abstract: A highly integrated 175-GHz 035-/spl mu/m CMOS transmitter is described The I/Q modulator-based transmitter facilitates integration through the use of a unique mixer, termed a harmonic-rejection mixer, and a wide loop bandwidth phase-locked loop (PLL) for the RF synthesizer The harmonic-rejection mixers are used to eliminate the need for a discrete IF filter and the use of a wide loop bandwidth PLL allowed for the complete integration of the synthesizers using low-Q components while achieving low phase noise The entire transmit signal path from the digital-to-analog converters to the power amplifier, including two fully integrated frequency synthesizers, is integrated into a single-chip solution The transmitter was tested with a testing buffer before the power amplifier (PA) and achieved less than 13/spl deg/ rms phase error when modulating a DCS-1800 GMSK signal The prototype consumed 151 mA from a 3-V supply A class-C PA, capable of driving 25 dBm off-chip, was included and the output was compared to the testing buffer with little change in the transmitter performance

Radiation hard silicon detectors—developments by the RD48 (ROSE) collaboration

Abstract: The RD48 (ROSE) collaboration has succeeded to develop radiation hard silicon detectors, capable to withstand the harsh hadron fluences in the tracking areas of LHC experiments. In order to reach this objective, a defect engineering technique was employed resulting in the development of Oxygen enriched FZ silicon (DOFZ), ensuring the necessary O-enrichment of about 2×1017 O/cm3 in the normal detector processing. Systematic investigations have been carried out on various standard and oxygenated silicon diodes with neutron, proton and pion irradiation up to a fluence of 5×1014 cm−2 (1 MeV neutron equivalent). Major focus is on the changes of the effective doping concentration (depletion voltage). Other aspects (reverse current, charge collection) are covered too and the appreciable benefits obtained with DOFZ silicon in radiation tolerance for charged hadrons are outlined. The results are reliably described by the “Hamburg model”: its application to LHC experimental conditions is shown, demonstrating the superiority of the defect engineered silicon. Microscopic aspects of damage effects are also discussed, including differences due to charged and neutral hadron irradiation.

LED driver circuit and method

Abstract: An LED driver circuit and method are disclosed where an array of light emitting diodes have a transistor connected to each respective array of light emitting diodes. A PWM controller has an input for receiving a voltage reference and an output connected to selected transistors for driving selected transistors and setting a PWM duty cycle for the selected arrays of light emitting diodes to determine the brightness of selected light emitting diodes. An oscillator is connected to the PWM controller for driving the PWM controller.

Precipitation behavior and its effect on strengthening of an HSLA-Nb/ti steel

Abstract: The precipitation behavior of a commercial high-strength low-alloy (HSLA) steel microalloyed with 0.086 wt pct Nb and 0.047 wt pct Ti has been investigated using transmission electron microscopy (TEM) and mechanical testing. The emphasis of this study is to compare an industrially hot-rolled steel and samples from a laboratory hot torsion machine simulation. From TEM observations, the Ti and Nb containing precipitates could be grouped according to their size and shape. The precipitates in order of size were found to be cubic TiN particles with sizes in the range of 1 µm, grain boundary precipitates with diameters of approximately 10 nm, and very fine spherical or needle-shaped precipitates with sizes on the order of 1 nm. The needlelike precipitates were found on dislocations in ferrite and constituted the dominant population in terms of density. Thus, they appear to be responsible for the precipitation strengthening observed in this steel. Aging tests were carried out at 650°C to evaluate the precipitate strengthening kinetics in detail. The strengthening mechanisms can be described with a nonlinear superposition of dislocation and precipitation hardening. The mechanical properties of torsion-simulated material and as-coiled industrial material are similar; however, there are some microstructural differences that can be attributed to the somewhat different processing routes in the laboratory as compared to hot strip rolling.

Preventing SPA/DPA in ECC Systems Using the Jacobi Form

Abstract: In this paper we show how using a representation of an elliptic curve as the intersection of two quadrics in P3 can provide a defence against Simple and Differental Power Analysis (SPA/DPA) style attacks. We combine this with a 'random window' method of point multiplication and point blinding. The proposed method offers considerable advantages over standard algorithmic techniques of preventing SPA and DPA which usually require a significant increased computational cost, usually more than double. Our method requires roughly a seventy percent increase in computational cost of the basic cryptographic operation, although we give some indication as to how this can be reduced. In addition we show that the Jacobi form is also more efficient than the standard Weierstrass form for elliptic curves in the situation where SPA and DPA are not a concern.

Noise filter for bayer pattern image data

Abstract: A method of filtering an image filter is disclosed. The filter is provided for a digital camera including image sensors sensitive to light, a color filter placed over sensitive elements of the sensors and patterned according to a Bayer mosaic pattern layout and an interpolation algorithm joining together the digital information provided by differently colored adjacent pixels in said Bayer pattern. The filter is adaptive and includes a noise level computation block for operating directly on a said Bayer pattern data set of for each color channel thus removing noise while simultaneously preserving picture detail.

Evolutionary Optimization Algorithms

Abstract: As pointed out in the previous chapters, both fuzzy logic and neural networks imply optimization processes. For fuzzy logic in particular, optimization algorithms are needed that will allow determinations of the number of rules, the number of fuzzy sets and their position in the universe of discourse to be based on optimum criteria instead of on empirical techniques. This process generally involves a large number of variables and thus requires particularly efficient optimization algorithms. Similarly, in the field of neural networks, what can be of considerable use are optimization algorithms capable of finding the global minimum of a function with many variables, in order to overcome the intrinsic limitations inherent in learning algorithms based on the gradient technique. Therefore, this chapter will describe evolutionary algorithms that seem to respond to the characteristics required by soft computing, both with regard to versatility and to the efficiency and goodness of the results obtained. Genetic algorithms have proved to be a valid procedure for global optimization, applicable in very many sectors of engineering [10–15]. Ease of implementation and the potentiality inherent in an evolutionist approach make genetic algorithms a powerful optimization tool for non-convex functions. The genetic algorithms (GA) represent a new optimization procedure based on Darwin’s natural evolution principle. Adopting this analogy, inside a population in continuous evolution, the individual who best adapts to environmental constraints corresponds to the optimal solution of the problem to be solved.

Dual mode smart card and associated methods

Abstract: A dual-mode IC is provided for operating in first mode such as an ISO mode in accordance with International Standards Organization 7816 (ISO 7816) protocol, and a second, non-ISO mode, such as a USB mode in accordance with Universal Serial Bus (USB) protocol. The dual-mode IC is preferably in a smart card and includes a microprocessor, a switching block, and an external interface. The external interface comprises a voltage supply pad, a reference voltage pad, a reset pad, a clock pad and an input/output pad in accordance with the ISO 7816 protocol, and a D-plus pad and D-minus pad in accordance with the USB protocol. The IC further includes a mode configuration circuit for detecting a USB mode condition on at least one of the D-plus and D-minus pads, and configuring the IC in the ISO mode or the USB mode depending on the result. Once the IC is configured in a particular mode, it will operate in only that mode until the next power-on reset sequence.

Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices

Abstract: In this paper, we propose a thorough experimental and theoretical investigation of memory-cell structures employing discrete-trap type storage nodes, using either natural nitride traps or semiconductor nano-crystals. thus operating with a small finite number of electrons. A detailed account of static and dynamic charging/discharging phenomena occurring in these devices is given, based on bias-, time-, and temperature-dependent measurements. A comprehensive interpretation of experimental results is proposed by means of physical modeling. In particular, two different models are proposed. The first one consists in a modified floating-gate-like approach, while the second one is a trap-like approach, relying on Shockley-Read-Hall statistics. Using these two approaches, some general behavior laws for memory operation are formulated. Considerations on the suitability of each model on the particular structures are suggested.

On-chip communication architecture for OC-768 network processors

Abstract: The need for network processors capable of forwarding IP packets at OC-192 and higher data rates has been well established. At the same time, there is a growing need for complex tasks, like packet classification and differentiated services, to be performed by network processors. At OC-768 data rate, a network processor has 9 nanoseconds to process a minimum-size IP packet. Such ultra high-speed processing, involving complex memory-intensive tasks, can only be achieved by multi-CPU distributed memory systems, using very high performance on-chip communication architectures. In this paper, we propose a novel communication network architecture for 8-CPU distributed-memory systems that has the potential to deliver the throughput required in next generation routers. We then show that our communication architecture can easily scale to accommodate much greater number of network nodes. Our network architecture yields higher performance than the traditional bus and crossbar yet has low implementation cost. It is quite flexible and can be implemented in either packet or circuit switched mode. We will compare and contrast our proposed architecture with busses and crossbars using metrics such as throughput and physical layout cost.

A high-efficiency driver circuit for capacitive loads

Abstract: The invention relates to a high-efficiency driver circuit for capacitive loads, which circuit comprises a drive portion (12) connected to at least one end (X) of a capacitive electric load (11) being applied a voltage waveform. Advantageously, this circuit further comprises a switching circuit portion (13) having its output connected to the above one end (X) of the capacitive load (11) in order to supply a fraction of the overall current demanded by the load (11). Briefly, the invention is a circuit arrangement aimed at providing a highly efficient drive for the capacitive load, using a combined linear/switching setup and without debasing the quality of the waveform generated across the capacitive load.

Apparatus and method for synchronizing video and audio MPEG streams in a video playback device

Abstract: There is disclosed an MPEG decoder comprising: 1) a packetized elementary stream (PES) interface for receiving a plurality of packetized elementary streams associated with a single video program; 2) a presentation time stamp (PTS) detection circuit for detecting presentation time stamps in the packetized elementary streams and extracting the presentation time stamps therefrom; and 3) a selection circuit for selecting presentation time stamps associated with a first one of the plurality of packetized elementary streams and transmitting the selected presentation time stamps to a clock generation circuit, wherein the clock generation circuit generates a first reference clock signal used by a first decoder to decode the first packetized elementary stream. The clock generation circuit further generates a second reference clock signal synchronized to the first reference clock signal, wherein the second reference clock signal is used by a second decoder to decode a second packetized elementary stream in synchronization with the first packetized elementary stream.

Scanning capacitive semiconductor fingerprint detector

Abstract: A scanning fingerprint detection system that includes an array of capacitive sensing elements. The array has a first dimension greater than the width of a fingerprint and a second dimension less than the length of a fingerprint. Each of the capacitive sensing elements has a size less than the width of a fingerprint ridge. Circuitry is provided for scanning the array to capture an image of a portion of fingerprint and for assembling the captured images into a fingerprint image as a fingerprint is moved over the array.

An eighth-order CMOS low-pass filter with 30-120 MHz tuning range and programmable boost

Abstract: A CMOS low-pass filter with programmable boost is presented. The architecture is a G/sub m//C type with the G/sub m/ value controlled through a resistor servo approach. The transfer function has been optimized in order to reduce the sensitivity to component parameter variations. The 1:4 tuning range is achieved by exploiting a dual-loop control over a degenerated differential pair. At the nominal output voltage swing of 200 mV/sub pp/ differential, a THD better than 40 dB is guaranteed. The high-frequency boost is programmable between 6 and 14 dB. This filter, realized as a cascade of biquad and first-order cells, is implemented in a 0.25-/spl mu/m 2.5-V CMOS technology. It dissipates 120 mW with f/sub c/=120 MHz and has a die area of 0.23 mm/sup 2/.

Multicast with cache (Mcache): an adaptive zero-delay video-on-demand service

Abstract: This paper presents a closed-loop (demand-driven) approach towards VoD services, called multicast with caching (Mcache). Servers use multicast to reduce bandwidth usage by serving multiple requests using a single data stream. However, this requires clients to delay receiving the movie until the multicast starts. Using regional cache servers, Mcache removes initial playout delays at the clients, because the clients can receive the prefix of a requested clip from regional caches while waiting for the multicast to start. In addition, the multicast containing the later portion of the movie can wait until the prefix is played out. While this use of caches has been proposed before, the novelty of our scheme lies in that the requests coming after the multicast starts can still be batched together to be served by multicast patches without any playout delays. The use of patches has been proposed to be used either with unicast or with playout delays. Mcache effectively hires the idea of a multicast patch with caches to provide a truly adaptive VoD service whose bandwidth usage is up to par with the best known open-loop schemes under high request rates while using only minimal bandwidth under low request rates. In addition, efficient use of multicast and caches removes the need for a priori knowledge of client request rates and client disk storage requirements which some of the existing schemes assume. This makes Mcache ideal for the current heterogeneous Internet environments where those parameters are hard to predict.

A sub-1-dB NF/spl plusmn/2.3-kV ESD-protected 900-MHz CMOS LNA

Abstract: A sub-1-dB noise figure HBM ESD-protected [-3 kV, 2.3 kV] low noise amplifier (LNA) has been integrated in a 0.35-/spl mu/m RF CMOS process with on-chip inductors. The sensitivity of the LNA performances to the spread of parasitics associated with package and bondwire has been attenuated by using an inductive on-chip source degeneration. At 920 MHz and P/sub dc/=8.6 mW, the LNA features: noise figure NF=1 dB, input return loss=-8.5 dB, output return loss=-27 dB, power gain G/sub p/=13 dB, input IIP3=-1.5 dBm. At a power dissipation of 5 mW and 17.6 mW, a NF respectively equal to 1.2 dB and 0.85 dB is measured. The CMOS LNA takes 12 pins of a TQFP48 package, an area of 1.0/spl times/0.66 mm/sup 2/ (bondwire pads excluded) and it is the first HBM ESD-protected [-3 kV, 2.3 kV] CMOS LNA to break the 1-dB NF barrier.

Textile-like capacitive pressure sensor and method of mapping the pressure exerted at points of a surface of a flexible and pliable object, particularly of a sail

Abstract: A device for detecting the pressure exerted at different points of a flexible and/or pliable object that may assume different shapes, includes a plurality of capacitive pressure sensors and at least a system for biasing and reading the capacitance of the sensors. The requirements of flexibility or pliability are satisfied by capacitive pressure sensors formed by two orthogonal sets of parallel or substantially parallel electrodes spaced, at least at each crossing between an electrode of one set and an electrode of the other set, by an elastically compressible dielectric, forming an array of pressure sensing pixel capacitors. The system for biasing and reading the capacitance includes column plate electrode selection circuits and row plate electrode selection circuits and a logic circuit for sequentially scanning the pixel capacitors and outputting pixel values of the pressure for reconstructing a distribution map of the pressure over the area of the array.

Developments for radiation hard silicon detectors by defect engineering—results by the CERN RD48 (ROSE) Collaboration

Abstract: This report summarises the final results obtained by the RD48 collaboration. The emphasis is on the more practical aspects directly relevant for LHC applications. The report is based on the comprehensive survey given in the 1999 status report (RD48 3rd Status Report, CERN/LHCC 2000-009, December 1999), a recent conference report (Lindstrom et al. (RD48), and some latest experimental results. Additional data have been reported in the last ROSE workshop (5th ROSE workshop, CERN, CERN/LEB 2000-005). A compilation of all RD48 internal reports and a full publication list can be found on the RD48 homepage (http://cern.ch/RD48/). The success of the oxygen enrichment of FZ-silicon as a highly powerful defect engineering technique and its optimisation with various commercial manufacturers are reported. The focus is on the changes of the effective doping concentration (depletion voltage). The RD48 model for the dependence of radiation effects on fluence, temperature and operational time is verified; projections to operational scenarios for main LHC experiments demonstrate vital benefits. Progress in the microscopic understanding of damage effects as well as the application of defect kinetics models and device modelling for the prediction of the macroscopic behaviour has also been achieved but will not be covered in detail.

A 2-dB noise figure 900-MHz differential CMOS LNA

Abstract: This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Since the devices of an inductively degenerated input stage are working in moderate inversion (at least at moderate power dissipation), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-/spl mu/m CMOS LNA (plus output buffer) prototype achieves the following performances: 2-dB noise figure (NF), 17.5-dB power gain, -6-dBm IIP3 with 8-mA current consumption from a 2.7-V voltage supply. To the author's knowledge, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an additional feature, this LNA has a programmable gain.

Apparatus and method for indexing MPEG video data to perform special mode playback in a digital video recorder and indexed signal associated therewith

Abstract: There is disclosed an apparatus for implementing special mode playback operations in a digital video recorder. The apparatus comprises an Intra frame indexing device capable of receiving an incoming MPEG video stream and identifying therein data packets associated with Intra frames, wherein the Intra frame indexing device modifies header information in a first data packet associated with a first Intra frame to include location information identifying a storage address of a second data packet associated with a second Intra frame.

Media player for distribution of music samples

Abstract: A method and apparatus of music distribution from a media player. A media player is provided with a “send to friend” icon. In one embodiment, when the icon is selected, a clipping of the currently playing music selection is taken from a predetermined location in the music selection and compressed using a fidelity reducing compression technique to produce a sample of the current selection suitable for distribution. The compressed clipping is sent to a selected recipient or recipients by email in the background while the music selection continues to play. The recipient(s) can be either a default recipient(s) or a recipient(s) selected from a list as in an address book application.

Method for merging digital images to obtain a high dynamic range digital image

Abstract: A method of processing digital source images, each represented by pixel matrices, to obtain from two or more source images, representing one and the same real scene and acquired by utilizing different exposure levels, a final digital image capable of reproducing the real scene with an exposure latitude greater than that of each of the source images. The method, which can be advantageously used in digital still cameras, produces the final image by combining the source images with the help of a weighted average constructed pixel by pixel. Thanks to a special filtering to which the weighting coefficients are subjected before the weighted mean operation, the method obtains a final image in which the source images are harmoniously combined with each other.

Apparatus for switching data in high-speed networks and method of operation

Abstract: A packet switch for switching cells comprising fixed-size data packets. The packet switch comprises: 1) N input ports for receiving and storing cells in input queues; 2) N output ports for receiving and storing cells from the N input ports in output queues; 3) a switch fabric for transferring the cells from the N input ports to the N output ports, the switch fabric comprising an internally buffered crossbar having N×N internal buffers, wherein each internal buffer is associated with a crosspoint of one of the N input ports and one of the N output ports; and 4) a scheduling controller for selecting a first one of a plurality of queued head-of-line (HOL) cells from the input queues to be transmitted to a first one of the N×N internal buffers according to a fair queuing algorithm in which each of the queued HOL cells is allocated a weight of R ij and wherein the scheduling controller selects a first one of a plurality of HOL cells buffered in a second one of the N×N internal buffers to be transmitted to a first one of the output queues according to a fair queuing algorithm in which each of the internally buffered HOL cells is allocated a weight of R ij .

Non-linear adaptive image filter for filtering noise such as blocking artifacts

Abstract: A filter reduces artifacts, such as grid noise and staircase noise, in block-coded digital images with image block boundaries. The type of filtering is determined after an estimation of the image global metrics and local metrics. For areas of the image near grid noise, the filter performs low pass filtering. For image fine details, such as edges and texture, no filtering is performed so that masking is avoided. The filter operates in intra-field mode and uses a fuzzy logic process, pixel deltas, and dual ramp generators to determine the horizontal and vertical length of a processing window surrounding an image block boundary.

Low-Energy FPGAs - Architecture and Design

Abstract: The book addresses the energy consumption of Field-Programmable Gate Arrays (FPGAs). FPGAs are becoming popular as embedded components in computing platforms. The programmability of the FPGA can be used to customize implementations of functions on an application basis. This leads to performance gains, and enables reuse of expensive silicon.

Multi-mode smart card, system and associated methods

Abstract: A multi-mode IC is provided for operating in a first mode such as an ISO mode in accordance with International Standards Organization 7816 (ISO 7816) protocol, and a second, non-ISO mode, such as a USB mode in accordance with Universal Serial Bus (USB) protocol. The multi-mode IC is preferably in a smart card and includes a microprocessor and an external interface. The external interface comprises a voltage supply pad, a ground pad, a first set of pads for the first mode, and 2 second set of pads for the second mode. The first set of pads preferably include a reset pad, a clock pad and an input/output pad in accordance with the ISO 7816 protocol, and may also include a variable supply voltage pad in accordance with the ISO 7816 protocol. The IC further includes a mode configuration circuit for detecting a mode condition on one pad of the first set of pads, and configuring the IC in the ISO mode or the non-ISO mode depending on the result. Once the IC is configured in a particular mode, it will operate in only that mode until the next power-on reset sequence.

Page-erasable flash memory

Abstract: The invention concerns a page-erasable flash memory (MEM1) comprising a memory plane (FMA) including a plurality of pages comprising each floating gate transistors connected by their gates to word lines (WL1), a word line decoder (XDEC1) connected to the memory word lines, and means for applying a positive erasing voltage (VER+) to the source or drain electrodes of all the floating gate transistors of a sector comprising a page to be erased. The invention is characterised in that the word line decoder (XDEC1) comprises means (ADi) for applying, during erasure of a page, a negative erasing voltage (VPOL, VER-) to the gates of the transistors of the page to be erased, while applying a positive inhibiting voltage (VINHIB, VPCX) to the gates of the transistors of at least one page not to be erased. The memory also comprises means controlling at least a page of the memory, designed to perform a first reading of the page by applying a first reading voltage (VREAD) to the gates of the transistors of the page, perform a second reading of the page by applying a second reading voltage (VVRFY) to the gates of the transistors of the page, and reprogram transistors of the page if the two readings yield different results (W1, W2).

Digital phase lock loop

Abstract: A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal. The digital frequency synthesizer also a non-glitching MUX electrically coupled to the digital DLL for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse glitch-free from the selected output tap, and a phase accumulator electrically coupled to the non-glitching MUX for precisely dividing a timing period of the input reference signal and for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse at a precise point in the timing period from the output tap. The digital phase detector, is electrically coupled to the digital frequency synthesizer to compare an edge of the input reference signal to an edge of a synthesized signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the synthesized signal.

Radiation effects on floating-gate memory cells

Abstract: We have addressed the problem of threshold voltage (V/sub TH/) variation in flash memory cells after heavy-ion irradiation by using specially designed array structures and test instruments. After irradiation, low V/sub TH/ tails appear in V/sub TH/ distributions, growing with ion linear energy transfer (LET) and fluence. In particular, high LET ions, such as iodine used in this paper, can produce a bit flip. Since the existing models cannot account for large charge losses from the floating gate, we propose a new mechanism, based on the excess of positive charge produced by a single ion, temporarily lowering the tunnel oxide barrier (positive charge assisted leakage current) and enhancing the tunneling current. This mechanism fully explains the experimental data we present.

Still picture format for subsequent picture stitching for forming a panoramic image

Abstract: A method for storing a plurality of still images to form a panoramic image. The method comprising the steps of receiving a first image forming a part of a series of images to form a panoramic image and storing the first image in memory. When one or more subsequent images after the first image are received the steps of calculating one or more panoramic parameters between a current image and a previous image stored in memory and storing the current image with the one or more panoramic parameters in memory are performed.