Showing papers by "STMicroelectronics published in 2004"

Electronic switching in phase-change memories

Abstract: A detailed investigation of electronic switching in chalcogenide-based phase-change memory devices is presented. An original bandgap model consistent with the microscopic structure of both crystalline and amorphous chalcogenide is described, and a physical picture of the switching mechanism is proposed. Numerical simulations provide, for the first time, a quantitative description of the peculiar current-voltage curve of a Ge/sub 2/Sb/sub 2/Te/sub 5/ resistor, in good agreement with measurements performed on test devices.

Dynamic multiobjective optimization problems: test cases, approximations, and applications

Abstract: After demonstrating adequately the usefulness of evolutionary multiobjective optimization (EMO) algorithms in finding multiple Pareto-optimal solutions for static multiobjective optimization problems, there is now a growing need for solving dynamic multiobjective optimization problems in a similar manner. In this paper, we focus on addressing this issue by developing a number of test problems and by suggesting a baseline algorithm. Since in a dynamic multiobjective optimization problem, the resulting Pareto-optimal set is expected to change with time (or, iteration of the optimization process), a suite of five test problems offering different patterns of such changes and different difficulties in tracking the dynamic Pareto-optimal front by a multiobjective optimization algorithm is presented. Moreover, a simple example of a dynamic multiobjective optimization problem arising from a dynamic control loop is presented. An extension to a previously proposed direction-based search method is proposed for solving such problems and tested on the proposed test problems. The test problems introduced in this paper should encourage researchers interested in multiobjective optimization and dynamic optimization problems to develop more efficient algorithms in the near future.

Novel /spl mu/trench phase-change memory cell for embedded and stand-alone non-volatile memory applications

Abstract: A novel cell structure for chalcogenide-based non-volatile Phase-Change Memories is presented. The new /spl mu/trench approach is fully compatible with an advanced CMOS technology, is highly manufacturable and allows to optimize array density and cell performance. Programming currents of 600 /spl mu/A, endurance of 10/sup 11/ programming cycles and data retention capabilities for 10 years at 110/spl deg/C have been demonstrated. The manufacturability is proven by experimental results from multi-megabit arrays.

Reliability study of phase-change nonvolatile memories

Abstract: A detailed investigation of the reliability aspects in nonvolatile phase-change memories (PCM) is presented, covering the basic aspects related to high density array NVM, i.e., data retention, endurance, program and read disturbs. The data retention capabilities and the endurance characteristics of single PCM cells are analyzed, showing that data can be stored for 10 years at 110/spl deg/C and that a resistance difference of two order of magnitude between the cell states can be maintained for more than 10/sup 11/ programming cycles. The main mechanisms responsible for instabilities just before failure as well as for final device breakdown are also discussed. Finally, the impact of read and program disturbs are clearly assessed, showing with experimental data and simulated results that the crystallization induced during the cell read out and the thermal cross-talk due to adjacent bits programming do not affect the retention capabilities of the PCM cells.

Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials

Abstract: A detailed investigation of the time evolution for the low-field resistance R/sub off/ and the threshold voltage V/sub th/ in chalcogenide-based phase-change memory devices is presented. It is observed that both R/sub off/ and V/sub th/ increase and become stable with time and temperature, thus improving the cell readout window. Relying on a microscopic model, the drift of R/sub off/ and V/sub th/ is linked to the dynamic of the intrinsic traps typical of amorphous chalcogenides, thus providing for the first time a unified framework for the comprehension of chalcogenide materials transient behavior.

Segment-based stereo matching using graph cuts

Abstract: In this paper we present a new segment-based stereo matching algorithm using graph cuts. In our approach, the reference image is divided into non-overlapping homogeneous segments and the scene structure is represented as a set of planes in the disparity space. The stereo matching problem is formulated as an energy minimization problem in the segment domain instead of the traditional pixel domain. Graph cuts technique is used to fast approximate the optimal solution, which assigns the corresponding disparity plane to each segment. Experiments demonstrate that the performance of our algorithm is comparable to the state-of-the-art stereo algorithms on various data sets. Furthermore, strong performance is achieved in the conventionally difficult areas such as: textureless regions, disparity discontinuous boundaries and occluded portions.

A fuzzy definition of "optimality" for many-criteria optimization problems

Abstract: When dealing with many-objectives optimization problems, the concepts of Pareto-optimality and Pareto-dominance are often inefficient in modeling and simulating human decision making. This leads to an unpractical size for the set of Pareto-optimal (PO) solutions, and an additional selection criteria among solutions is usually arbitrarily considered. In the paper, different fuzzy-based definitions of optimality and dominated solutions, being nonpreference based, are introduced and tested on analytical test cases, in order to show their validity and nearness to human decision making. Based on this definitions, different subsets of PO solution set can be computed using simple and clear information provided by the decision maker and using a parameter value ranging from zero to one. When the value of the above parameter is zero, the introduced definitions coincide with classical Pareto-optimality and dominance. When the parameter value is increased, different subset of PO solutions can be obtained corresponding to higher degrees of optimality.

Plasma wave detection of sub-terahertz and terahertz radiation by silicon field-effect transistors

Abstract: We report on experiments on photoresponse to sub-THz (120GHz) radiation of Si field-effect transistors (FETs) with nanometer and submicron gate lengths at 300K. The observed photoresponse is in agreement with predictions of the Dyakonov–Shur plasma wave detection theory. This is experimental evidence of the plasma wave detection by silicon FETs. The plasma wave parameters deduced from the experiments allow us to predict the nonresonant and resonant detection in THz range by nanometer size silicon devices—operating at room temperature.

Electronic switching effect and phase-change transition in chalcogenide materials

Abstract: The threshold switching mechanism in amorphous chalcogenides is investigated, showing experimental data that once and for all demonstrate its electronic nature. The physical mechanisms responsible for the switching to the highly conductive state are discussed and the impact of cumulative read-out pulses is also investigated, showing that phase-change transitions induced by usual reading operations in phase-change memory cells are completely negligible.

Analyzing on-chip communication in a MPSoC environment

Abstract: This work focuses on communication architecture analysis for multi-processor systems-on-chips (MPSoCs), and it leverages a SystemC-based platform to simulate a complete multi-processor system at the cycle-accurate and signal-accurate level. These features allow to stimulate the communication sub-system with functional traffic generated by real applications running on top of a configurable number of ARM processors. This opens up the possibility for communication infrastructure exploration and for the investigation of its impact on system performance at the highest level of accuracy. Our simulation environment proved capable of a detailed comparative analysis between two industry-standard communication architectures, under realistic workloads and different system configurations, pointing out the impact of fine grained architectural mismatches on macroscopic performance differences.

A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications

Abstract: A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-/spl mu/m standard digital CMOS technology a fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has an area of 3.4 mm/sup 2/ PADs included, and it consumes 28 mW. With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 /spl mu/s. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered) fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer could be used also for TX direct modulation over a broad band. The choice of such a large bandwidth, however, still limits the spur performance. A slightly smaller bandwidth would fulfill WCDMA requirements. This has been shown in a second prototype, using the same architecture but employing an external loop filter and VCO for greater flexibility and ease of testing.

Depth map generation by image classification

Abstract: This paper presents a novel and fully automatic technique to estimate depth information from a single input image. The proposed method is based on a new image classification technique able to classify digital images (also in Bayer pattern format) as indoor, outdoor with geometric elements or outdoor without geometric elements. Using the information collected in the classification step a suitable depth map is estimated. The proposed technique is fully unsupervised and is able to generate depth map from a single view of the scene, requiring low computational resources.

Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact

Abstract: Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross-section and dye penetration test.

An 8Mb demonstrator for high-density 1.8V Phase-Change Memories

Abstract: An 8Mb Non-Volatile Memory Demonstrator incorporating a novel 0.32 /spl mu/m/sup 2/ Phase-Change Memory (PCM) cell using a Bipolar Junction Transistor (BJT) as selector and integrated into a 3V 0.18 /spl mu/m CMOS technology is presented. Realistically large 4Mb tiles with a voltage regulation scheme that allows fast bitline precharge and sense are proposed. An innovative approach that minimizes the array leakage has been used to verify the feasibility of high-density PCM memories with improved Read/Write performance compared to Flash. Finally, cells distributions and first endurance measurements demonstrate the chip functionality and a good working window.

Analysis of phase distribution in phase-change nonvolatile memories

Abstract: The phase transformation in chalcogenide-based nonvolatile memories is studied by cell electrical characterization. The cell state (amorphous, crystalline, or mixed) is changed by applying electrical pulses, then the cell resistance R and the current-voltage characteristics are measured. From the analysis of the electrical parameters of the cell, we provide evidence for a stacked-like phase distribution in the active layer. Results are discussed with reference to the thermal profile during the program pulse in the chalcogenide layer.

Scan Design and Secure Chip

Abstract: Testing a secure system is often considered as a severebottleneck. While testability requires to an increase inboth observability and controllability, secure chips aredesigned with the reverse in mind, limiting access to chipcontent and on-chip controllability functions. As a result,using usual design for testability techniques whendesigning secure ICs may seriously decrease the level ofsecurity provided by the chip. This dilemma is even moresevere as secure applications need well-tested hardwareto ensure that the programmed operations are correctlyexecuted. In this paper, a security analysis of the scantechnique is performed. This analysis aims at pointing outthe security vulnerability induced by using such a DfTtechnique. A solution securing the scan is finally proposed.

Poly-gate replacement through contact hole (PRETCH): a new method for high-k/metal gate and multi-oxide implementation on chip

Abstract: We report on a new concept for an easy co-integration, on a same chip, of different MOSFET configurations (GP, LP, HS, buffer transistors) realized after the end of the standard FE process. This poly-gate replacement through contact hole (PRETCH) concept enables replacement of initial poly-silicon gate and/or gate oxide by any gate stack desired. PRETCH addresses multi-Vt control, multi-oxide realization and metal gate integration challenges. As PRETCH gate replacement takes place after PMD (beginning of BE), it is perfectly suitable for high-K integration, allowing low thermal budget (no source and drain anneal seen by HK) and no particular contamination issues. Large potential of PRETCH integration is confirmed by promising morphological results and by very good electrical characteristics of both nMOS and pMOS TiN 90nm gate length MOSFETs. Integration of TiN gate with three different oxide configurations is demonstrated: initial thermal oxide left, replaced by either slot plane antenna [SPA] oxide or high-K. PRETCH concept has also been validated on 3D architectures such as DG. Finally, functional TiN DG inverters and SRAMs are demonstrated.

Mechanical characterization of polysilicon through on-chip tensile tests

Abstract: Two new types of on-chip tests have been designed in order to evaluate the elastic Young modulus and the fracture strength of polysilicon used in microelectromechanical systems (MEMS). The former is a pure tension test, while the latter is a single-edge-notched tension test. The actuation in both tests is obtained by means of an ad hoc designed layout of parallel plates capacitors applying sufficiently high forces to reach significant strains in the tensile specimens and complete failure of the notched specimens. The pure tension tests on 20 specimens showed a low dispersion and gave a Young modulus for the polysilicon of 143 GPa. A total of 92 notched specimens were tested up to failure. The experimental results, supported by finite-element simulations, gave a value of the maximum stress for the notched specimens in the range 4144-4568 MPa.

A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM

Abstract: A 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time. The device architecture is fully compatible with CMOS logic process integration, allowing very low chip cost for SoC applications. Experimental results show a retention time over 1s at 25/spl deg/C and 100ms at 85/spl deg/C, which is compatible with eDRAM requirements. Non-destructive readout is experimentally demonstrated at 85/spl deg/C. The integration of the memory cell in a matrix arrangement is evaluated. Gate and drain disturb are characterized, showing enough disturb margins for memory operations.

Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide

Abstract: This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. negative bias temperature instability (NBTI) and positive bias temperature instability in both NMOS and PMOS have been compared and a possible explanation for all configurations has been suggested. Recovery and temperature effect under NBTI were also investigated showing different behaviors of the two components.

An adaptive, self-organizing dynamical system for hierarchical control of bio-inspired locomotion

Abstract: In this paper, dynamical systems made up of locally coupled nonlinear units are used to control the locomotion of bio-inspired robots and, in particular, a simulation of an insect-like hexapod robot. These controllers are inspired by the biological paradigm of central pattern generators and are responsible for generating a locomotion gait. A general structure, which is able to change the locomotion gait according to environmental conditions, is introduced. This structure is based on an adaptive system, implemented by motor maps, and is able to learn the correct locomotion gait on the basis of a reward function. The proposed control system is validated by a large number of simulations carried out in a dynamic environment for simulating legged robots.

Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress

Abstract: This paper presents an electrical analysis of mechanical stress induced by shallow trench isolation (STI) on MOSFETs of advanced 0.13 /spl mu/m bulk and silicon-on-insulator (SOI) technologies. By applying external calibrated stress, we present piezoresistive coefficients measurements on these technologies, and we compare small and long transistors electrical responses, evidencing the strong effect of source drain resistance R/sub sd/. Then, using the same approach on short devices with different gate-edge-to-STI distances, we quantitatively evaluate stress profile induced by STI and its mean value under the gate of the devices. Results are discussed to explain differences between bulk and SOI technologies, as well as between nMOS and pMOS. We show that the observed higher pMOS drain current shift is related to the process, and may be explained by doping amorphization and recrystallization effects, and not by a piezoresistive coefficient difference as usually assumed.

Segment based image matching method and system

Abstract: An image matching method and system for use with multiple images of a scene captured from different angles. Image matching is performed by identifying a plurality of segments within at least two images, determining an initial disparity values for pixels in the images and then determining initial disparity planes for the segments by fitting a plane to initial disparity values for the segments. A refined disparity plane set is created by iteratively refitting the disparity planes by using various fitting cost functions and weighted linear systems. A labeling of each segment to a disparity plane is made by minimizing a global energy function that includes energy terms for segment to disparity plane matching as well as penalizing disparity plane discontinuities between adjacent image segments.

Passivation mechanisms in cryogenic SF6/O2 etching process

Abstract: Passivation mechanisms of Si trenches involved in SF6/O2 cryogenic plasma etching were investigated in order to better control the process and avoid defects. Trench sidewalls and profiles were ex situ characterized geometrically by SEM and chemically by spatially resolved XPS experiments. These measurements reveal that the passivating layer is removed during the increase of the wafer chuck temperature leading to a very clean surface of the sidewalls after processing. Nearly no SiO2 formation on the sidewalls was observed after the very low temperature etching (−100 °C). A two-step process was defined to rebuild the passivating layer after its destruction and continue the trench etching. The necessary conditions for properly rebuilding the passivating layer give precious information about its chemical composition. These experiments clearly show that sulfur is not a necessary element to form an efficient passivating layer.

A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories

Abstract: A capacitor-less DRAM cell on very thin film (Tsi=16nm) and short gate length (Lg=75nm) fully depleted (FD) device is demonstrated for the first time. Memory operations mechanisms are presented and retention time compatible to eDRAM requirements is measured at 85/spl deg/C. Nondestructive reading is demonstrated at 25/spl deg/C and disturb margins are deeply investigated, showing the possibility of matrix integration. This study is then extended to another type of FD device: the very promising double gate architecture.

Novel numerical and experimental analysis of dynamic responses under board level drop test

Abstract: Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. A novel input acceleration (input-G) method is developed to simulate the exact drop test process using ANSYS-LSDYNA software. The model can be applied to simulate the overall impact responses including PCB cyclic bending, which are very critical for understanding of board level drop test.

Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)

Abstract: In this paper, an overview of today's status and progress, as well as tomorrow's challenges and trends, in the field of advanced nonvolatile memories based on discrete traps is given. In particular, unique features of silicon nanocrystal and SONOS memories will be illustrated through original recent data. The main potentials and main issues of these technologies as candidates to push further the scaling limits of conventional floating-gate Flash devices will be evaluated.