Showing papers by "STMicroelectronics published in 2006"

Plasma wave detection of terahertz radiation by silicon field effects transistors: Responsivity and noise equivalent power

Abstract: Si metal oxide semiconductor field effect transistors (MOSFETs) with the gate lengths of 120–300nm have been studied as room temperature plasma wave detectors of 0.7THz electromagnetic radiation. In agreement with the plasma wave detection theory, the response was found to depend on the gate length and the gate bias. The obtained values of responsivity (⩽200V∕W) and noise equivalent power (⩾10−10W∕Hz0.5) demonstrate the potential of Si MOSFETs as sensitive detectors of terahertz radiation.

Method of managing fails in a non-volatile memory device and relative memory device

Abstract: A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. Each block including at least one failed cell in the first subset is located during a test on wafer of the non-volatile memory device. Each block is marked as bad, and a bad block address table of respective codes is stored in a non-volatile memory buffer. At power-on, the bad block address table is copied from the non-volatile memory buffer to the random access memory. A block of memory cells of the first subset is verified as bad by looking up the bad block address table, and if a block is bad, then remapping access to a corresponding block of redundancy cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.

A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications

Abstract: A 90nm technology node phase change memory (PCM) process, based on a chalcogenide material storage element with a vertical pnp bipolar junction transistor (BJT) selector device, is presented. The small cell area of 12F2, the good electrical results, and the intrinsic reliability demonstrate the viability of the PCM cell concept. Programming currents as low as 400muA, very good distributional data achieved on multi-megabit arrays for programming (set and reset), endurance, and retention, demonstrate the suitability of PCM for fabrication of a high density array at 90nm

The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

Abstract: This paper provides evidence that, as a result of constant-field scaling, the peak fT (approx. 0.3 mA/mum), peak fMAX (approx. 0.2 mA/mum), and optimum noise figure NFMIN (approx. 0.15 mA/mum) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers

Single-chip CMOS pulse generator for UWB systems

Abstract: This paper presents a single-chip pulse generator developed for Ultra Wide Band (UWB) wireless communication systems based on impulse radio technology. The chip has been integrated in a CMOS 130-nm technology with a single supply voltage of 1.2 V. The basic concept is to combine different delayed edges in order to form a very short duration "logical" pulse, and then filter it, so as to obtain an UWB pulse. It is possible to vary the output pulse shape, and thus the corresponding spectrum, just by acting on the delayed edge combination. Furthermore, the pulse generator supports both position modulation (2-PPM) and polarity modulation (BPSK modulation) in order to convey data through the air. Its power consumption remains less than 10 mW for a raw data rate of up to 160 Mb/s. Spectral and temporal measurements of the single-chip pulse generator are presented with an illustration of the modulation effects on the power spectral density (PSD)

Ozone-Based Atomic Layer Deposition of Alumina from TMA: Growth, Morphology, and Reaction Mechanism

Abstract: We examine the effect of growth temperature in the 150−300 °C range on the structural and morphological properties of Al2O3 films deposited using atomic layer deposition, contrasting the effect of H2O and O3 as oxygen sources. Trimethylaluminum (TMA) is the metal source. A mechanism for the O3 reaction is investigated using ab initio calculations and provides an explanation for the observed temperature dependence. The simulations show that hydroxyl groups are produced at the surface by the oxidation of adsorbed methyl groups by O3. This is confirmed by the measured rates; both H2O and O3 processes show molar growth rates per cycle that decrease with increasing reactor temperature, consistent with a decrease in hydroxyl coverage. At no temperature does the O3 process deposit more Al2O3 per cycle than the H2O process. Morphological characterization shows that O3 as the oxygen source yields lower-quality films than H2O; the films are less dense and rougher, especially at low growth temperatures. The existenc...

Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

Abstract: Electron and hole mobility in HfO/sub 2//metal gate MOSFETs is deeply studied through low-temperature measurements down to 4.2 K. Original technological splits allow the decorrelation of the different scattering mechanisms. It is found that even when charge trapping is negligible, strong remote coulomb scattering (RCS) due to fixed charges or dipoles causes most of the mobility degradation. The effective charges are found to be located in the HfO/sub 2/ near the SiO/sub 2/ interface within 2 nm. Experimental results are well reproduced by RCS calculation using 7/spl times/10/sup 13/ cm/sup -2/ fixed charges at the HfO/sub 2//SiO/sub 2/ interface. We also discuss the role of remote phonon scattering in such gate stacks. Interactions with surface soft-optical phonon of HfO/sub 2/ are clearly evidenced for a metal gate but remain of second order. All these remote interactions are significant for an interfacial oxide thickness up to 2 nm, over which, these are negligible. Finally, the metal gate (TiN) itself induces a modified surface-roughness term that impacts the low to high effective field mobility even for the SiO/sub 2/ gate dielectric references.

Radio frequency digital-to-analog converter

Abstract: A radio frequency digital-to-analog converter with a programmable current output. In exemplary aspects of the invention, improved apparatus and methods for providing (i) current mirror matching, (ii) enhanced current pulse rising edge performance, (ii) reduced base voltage swing, and (iv) compensated high voltage swing, are provided. The foregoing apparatus and methods can be applied to any RF signal application (wireless or otherwise), including for example wireless cellular handsets.

Quantum Cryptography and Secret-Key Distillation

Abstract: Quantum cryptography (or quantum key distribution) is a state-of-the-art technique that exploits properties of quantum mechanics to guarantee the secure exchange of secret keys. This 2006 text introduces the principles and techniques of quantum cryptography, setting it in the wider context of cryptography and security, with specific focus on secret-key distillation. The book starts with an overview chapter, progressing to classical cryptography, information theory (classical and quantum), and applications of quantum cryptography. The discussion moves to secret-key distillation, privacy amplification and reconciliation techniques, concluding with the security principles of quantum cryptography. The author explains the physical implementation and security of these systems, enabling engineers to gauge the suitability of quantum cryptography for securing transmission in their particular application. With its blend of fundamental theory, implementation techniques, and details of recent protocols, this book will be of interest to graduate students, researchers, and practitioners in electrical engineering, physics, and computer science.

Grain size effects on the dielectric constant of CaCu3Ti4O12 ceramics

Abstract: The CaCu3Ti4O12 (CCTO) compound shows an unusually high and almost temperature independent dielectric constant at low frequencies. CCTO powders have been synthesized by an organic gel-assisted citrate process. The ceramic microstructure was optimized for a given sintering process. Both the grain size and density are shown to be maximum when PVA is introduced in powder before the complete formation of CCTO. A correlated increase of the dielectric constant is evidenced by impedance spectroscopy measurements. Results support the IBLC model proposed to explain the high dielectric constant of CCTO.

Unbounded page-based transactional memory

Abstract: Exploiting thread level parallelism is paramount in the multicore era Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model Virtualized transactions (unbounded in space and time) are desirable, as they can increase the scope of transactions' use, and thereby further simplify a programmer's job However, hardware support is essential to support efficient execution of unbounded transactions In this paper, we introduce Page-based Transactional Memory to support unbounded transactions We combine transaction bookkeeping with the virtual memory system to support fast transaction conflict detection, commit, abort, and to maintain transactions' speculative data

Factors that impact the critical charge of memory elements

Abstract: In the current paper we investigate the factors that affect the critical charge (Q/sub crit/) for a soft error in a memory cell. Also the spread of Q/sub crit/ due to variations in the transistor model parameters is studied. The role of the current waveform that is applied in the simulation, the current pulse width, and the inclusion of back-end parasitics are discussed. Furthermore, we treat the impact on Q/sub crit/ of supply voltage, temperature, and process variant. Also, the paper deals with the effects of parameter variations through the node capacitance and the PMOS ON-current. Finally, we show the importance of the spread in Q/sub crit/ and demonstrate that detailed knowledge about the current-pulse width is necessary for accurate SER estimation.

Strained Si, Ge, and Si 1-x Ge x alloys modeled with a first-principles-optimized full-zone k∙p method

Abstract: The electronic energy band structure of strained and unstrained Si, Ge, and $\mathrm{SiGe}$ alloys is examined in this work using a 30-level $\mathbit{k}∙\mathbit{p}$ analysis. The energy bands are at first obtained with ab initio calculations based on the local-density approximation of density-functional theory, including a $GW$ correction and relativistic effects. The so-calculated band structure is then used to extract the unknown $\mathbit{k}∙\mathbit{p}$ fitting parameters with a conjugate-gradient optimization procedure. In a similar manner, the results of ab initio calculations for strained materials are used to fit the unknown deformation potentials that are included in the present $\mathbit{k}∙\mathbit{p}$ Hamiltonian following the Pikus-Bir correction scheme. We show that the present $\mathbit{k}∙\mathbit{p}$ model is an efficient numerical method, as far as computational time is concerned, which reproduces accurately the overall band structure, as well as the bulk effective density of states and the carrier effective masses, for both strained and unstrained materials. As an application, the present 30-level $\mathbit{k}∙\mathbit{p}$ model is used to describe the band offsets and the variations of the carrier effective masses in the strained ${\mathrm{Si}}_{1\ensuremath{-}x}{\mathrm{Ge}}_{x}∕{\mathrm{Si}}_{1\ensuremath{-}y}{\mathrm{Ge}}_{y}$ system.

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

Abstract: A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced.

Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction device for hybrid Magnetic-CMOS design

Abstract: The development of hybrid Magnetic-CMOS circuits such as MRAM (Magnetic RAM) and Magnetic logic circuit requires efficient simulation models for the magnetic devices. A macro-model of Magnetic Tunnel Junction (MTJ) is presented in this paper. This device is the most commonly used magnetic components in CMOS circuits. This model is based on Spin-Transfer Torque (STT) writing approach. This very promising approach should constitute the second generation of MRAM switching technology; it features small switching current (~120uA) and high programming speed (<1ns). The macro-model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform with Spectre 5.0.32 simulator. Many experimental parameters are integrated in this model to improve the simulation accuracy. So, the model can efficiently be used to design hybrid Magnetic CMOS circuits.

Substrate-level assembly for an integrated device, manufacturing process thereof and related integrated device

Abstract: In a substrate-level assembly (22), a device substrate (20) of semiconductor material has a top face (20a) and houses a first integrated device (1; 16), in particular provided with a buried cavity (3), formed within the device substrate (20), and with a membrane (4), suspended over the buried cavity (3) in the proximity of the top face (20a). A capping substrate (21) is coupled to the device substrate (20) above the top face (20a) so as to cover the first integrated device (1; 16), in such a manner that a first empty space (25) is provided above the membrane (4). Electrical-contact elements (28a, 28b) electrically connect the integrated device (1; 16) with the outside of the substrate-level assembly (22). In one embodiment, the device substrate (20) integrates at least a further integrated device (1', 10) provided with a respective membrane (4'); and a further empty space (25'), fluidically isolated from the first empty space (25), is provided over the respective membrane (4') of the further integrated device (1', 10).

A new gate driver integrated circuit for IGBT devices with advanced protections

Abstract: The aim of this paper is to discuss new solutions in the design of insulated gate bipolar transistor (IGBT) gate drivers with advanced protections such as two-level turn-on to reduce peak current when turning on the device, two-level turn-off to limit over-voltage when the device is turned off, and an active Miller clamp function that acts against cross conduction phenomena. Afterwards, we describe a new circuit which includes a two-level turn-off driver and an active Miller clamp function. Tests and results for these advanced functions are discussed, with particular emphasis on the influence of an intermediate level in a two-level turn-off driver on overshoot across the IGBT.

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

Abstract: The paper presents the DSPIN micro-network, that is an evolution of the SPIN architecture DSPIN is a scalable packet switching micro-network dedicated to GALS (Globally Asynchronous, Locally Synchronous) clustered, multi-processors, systems on chip The DSPIN architecture has a very small foot-print and provides to the system designer both guaranteed latency, and guaranteed throughput services for real-time applications

A Novel Soft-Output Layered Orthogonal Lattice Detector for Multiple Antenna Communications

Abstract: This paper presents a soft-output lattice detector algorithm for multiple-input multiple-output (MIMO) communications called layered orthogonal lattice detector (LORD). LORD adopts a new lattice formulation and relies on a channel orthogonalization process. Building on the optimality of LORD for two transmit antennas this paper is a generalization of the algorithm to any number of transmit antennas. The most interesting aspect of LORD is that for two transmit antennas max-log bit soft-output information can be simply generated and for greater than two antennas approximate max-log detection is achieved with reasonable complexity. LORD can be implemented in a parallel fashion, as desirable for VLSI. Extensive simulation results in different scenarios of interest for next generation WLANs (IEEE 802.11n) are reported. The simulations show that LORD is able to achieve very high signal-to-noise ratio (SNR) gains compared to current practical soft-output MIMO detectors.

Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

Abstract: The MultiFlex system is an application-to-platform mapping tool that integrates heterogeneous parallel components-H/W or S/W- into a homogeneous platform programming environment. This leads to higher quality designs through encapsulation and abstraction. Two high-level parallel programming models are supported by the following MultiFlex platform mapping tools: a distributed system object component (DSOC) object-oriented message passing model and a symmetrical multiprocessing (SMP) model using shared memory. We demonstrate the combined use of the MultiFlex multiprocessor mapping tools, supported by high-speed hardware-assisted messaging, context-switching, and dynamic scheduling using the StepNP demonstrator multiprocessor system-on-chip platform, for two representative applications: 1) an Internet traffic management application running at 2.5 Gb/s and 2) an MPEG4 video encoder (VGA resolution, at 30 frames/s). For these applications, a combination of the DSOC and SMP programming models were used in interoperable fashion. After optimization and mapping, processor utilization rates of 85%-91% were demonstrated for the traffic manager. For the MPEG4 decoder, the average processor utilization was 88%

Extended Dynamic Range From a Combined Linear-Logarithmic CMOS Image Sensor

Abstract: A CMOS image sensor that can operate in both linear and logarithmic mode is described. Two sets of data are acquired and combined in the readout path to render a high dynamic range image. This is accomplished in real-time without the use of frame memory. A dynamic range in excess of 120 dB was achieved at 26 frames/s (352times288-array). The system addresses the problems of high fixed pattern noise (FPN), slow response time, and low signal-to-noise ratio (SNR) in logarithmic mode. FPN has been effectively reduced by single and two parameter calibration, the latter achieving FPN of 2% per decade. A novel on-chip method of deriving a reference point has been implemented. The system is fabricated in a 0.18-mum 1P4M process and achieves a pixel pitch of 5.6 mum with 7 transistors per pixel

A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput

Abstract: A 4Gb 2b/cell NAND flash memory designed in a 90nm CMOS technology incorporates a 25MHz BCH ECC architecture, correcting up to 5 errors over a flexible data field (1B to 2102B). Two alternative Chien circuits are used depending on the number of errors (1 to 5) thus minimizing latency time. ECC area overhead is less than 1%

Method of inter-system coexistence and spectrum sharing for dynamic spectrum access networks-on-demand spectrum contention

Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and more particularly to a method of addressing inter-systems (cells) coexistence and spectrum sharing. The described method of spectrum sharing called On-Demand Spectrum Contention, integrates Dynamic Frequency Selection and Transmission Power Control with iterative on-demand spectrum contentions and provides fairness, adaptability, and efficiency of spectrum access for dynamic spectrum access systems using active inter-system coordination.

Advanced Numerical and Experimental Techniques for Analysis of Dynamic Responses and Solder Joint Reliability During Drop Impact

Abstract: Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e., crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints, dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when the PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross section and dye penetration tests

Quantum Short-channel Compact Modelling of Drain-Current in Double-Gate MOSFET

Abstract: A continuous compact model for the drain current, including short-channel effects and carrier quantization in Double-Gate MOSFET is developed. The model is particularly well-adapted to ultra-scaled devices, with short channel lengths and ultra-thin silicon films. An extensive comparison step with 2D quantum numerical results fully validates the model. The model is also shown to reproduce with an excellent accuracy experimental drain current in Double-Gate devices. Finally, the drain current model has been supplemented by a node charge model and the resulting DG model has been successfully implemented in Eldo IC analog simulator, demonstrating the application of the model to circuit simulation.

Method and system for dynamic spectrum allocation, and computer program product therefor

Abstract: A communication network such as a cellular network or a WLAN includes a set of user terminals. Within the communication network, a system dynamically controls spectrum usage. The system includes a functionality sensor for sensing spectrum usage within the area covered by the communication network, and a policy server for producing, as a function of the sensed spectrum usage, spectrum usage policies for the communication network. A broadcasting arrangement broadcasts the spectrum usage policies to the user terminals. The system is applicable to cognitive radio systems.

Radio frequency device with magnetic element, method for making such a magnetic element

Abstract: The invention concerns a radio frequency device comprising an electrically conductive element associated with at least one first continuous magnetic element including a substrate coated with a magnetic film having a granular structure with grains inclined relative to the normal to the substrate or a fibrous texture inclined relative to the normal to the substrate.