Showing papers by "STMicroelectronics published in 2009"

IEEE 802.22: The first cognitive radio wireless regional area network standard

Abstract: This article presents a high-level overview of the IEEE 802.22 standard for cognitive wireless regional area networks (WRANs) that is under development in the IEEE 802 LAN/MAN Standards Committee.

A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage

Abstract: In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge2-Sb2-TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure.

Thickness-dependent reversible hydrogenation of graphene layers.

Abstract: In this work, graphene layers on SiO2/Si substrate have been chemically decorated by radio frequency hydrogen plasma Hydrogen coverage investigation by Raman spectroscopy and micro-X-ray photoelectron spectroscopy characterization demonstrates that the hydrogenation of single layer graphene on SiO2/Si substrate is much less feasible than that of bilayer and multilayer graphene Both the hydrogenation and dehydrogenation process of the graphene layers are controlled by the corresponding energy barriers, which show significant dependence on the number of layers The extent of decorated carbon atoms in graphene layers can be manipulated reversibly up to the saturation coverage, which facilitates engineering of chemically decorated graphene with various functional groups viaplasma techniques

Multiple-rate low-density parity-check codes with constant blocklength

Abstract: This paper describes and analyzes low-density parity-check code families that support variety of different rates while maintaining the same fundamental decoder architecture. Such families facilitate the decoding hardware design and implementation for applications that require communication at different rates, for example to adapt to changing channel conditions. Combining rows of the lowest-rate parity-check matrix produces the parity-check matrices for higher rates. An important advantage of this approach is that all effective code rates have the same blocklength. This approach is compatible with well known techniques that allow low-complexity encoding and parallel decoding of these LDPC codes. This technique also allows the design of programmable analog LDPC decoders. The proposed design method maintains good graphical properties and hence low error floors for all rates.

A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration

Abstract: We present the first experimental study of a Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6nm-diameter). The technology is also extended to an independent double gate memory architecture, called φ-Flash. The experimental results with 6nm nanowires show high programming windows (up to 7.4V), making the structure compatible with multilevel operation. Excellent retention even after 104 cycles is achieved. The independent double gate option has otherwise been successfully integrated with 4-level stacked nanowires for multibit applications. The φ-Flash exhibits up to 1.8V ΔV Th between its two gates, demonstrating multibits operation. The basic process to fully disconnect the different nanowires in view of a full 3D integration of a memory array is discussed.

A 25 dBm Digitally Modulated CMOS Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control

Abstract: A digitally modulated power amplifier (DPA) in 1.2 V 0.13 mum SOI CMOS is presented, to be used as a building block in multi-standard, multi-band polar transmitters. It performs direct amplitude modulation of an input RF carrier by digitally controlling an array of 127 unary-weighted and three binary-weighted elementary gain cells. The DPA is based on a novel two-stage topology, which allows seamless operation from 800 MHz through 2 GHz, with a full-power efficiency larger than 40% and a 25.2 dBm maximum envelope power. Adaptive digital predistortion is exploited for DPA linearization. The circuit is thus able to reconstruct 21.7 dBm WCDMA/EDGE signals at 1.9 GHz with 38% efficiency and a higher than 10 dB margin on all spectral specifications. As a result of the digital modulation technique, a higher than 20.1 % efficiency is guaranteed for WCDMA signals with a peak-to-average power ratio as high as 10.8 dB. Furthermore, a 15.3 dBm, 5 MHz WiMAX OFDM signal is successfully reconstructed with a 22% efficiency and 1.53% rms EVM. A high 10-bit nominal resolution enables a wide-range TX power control strategy to be implemented, which greatly minimizes the quiescent consumption down to 10 mW. A 16.4% CDMA average efficiency is thus obtained across a > 70 dB power control range, while complying with all the spectral specifications.

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

Abstract: We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at I off = 300 pA/µm, V DD = 0.9V, and L G = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low V T variability is achieved with A Vt of 1.25 mV·µm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

A 32x32 50ps Resolution 10 bit Time to Digital Converter Array in 130nm CMOS for time Correlated Imaging

Abstract: (SUMMARY e report the design and characterisation of a 32x32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50μm pitch TDC array exhibits a minimum time resolution of 50ps, with accuracy of ±0.5 LSB DNL and 2.4 LSB INL. Process, voltage and temperature compensation (PVT) is achieved by locking the array to a stable external clock. The resulting time correlated pixel array is a viable candidate for single photon counting (TCSPC) applications such as fluorescent lifetime imaging microscopy (FLIM), nuclear or 3D imaging and permits scaling to larger array formats.

Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature

Abstract: Channel Hot-Carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias V BS . A three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the V GS , V DS (V BS ) conditions as a single I DS lifetime dependence is observed with V GD > 0. This gives a new age(t) function useful for accurate DC to AC transfers. Positive temperature activation is explained by the rise of ionization rate with electron-electron scattering (medium I DS ) and multi vibrational excitation (higher I DS ) which increase the H desorption by thermal emission. The use of forward VBS has shown no gain under CHC for both device types. The main limitation occurs under reverse V BS = −V DD in IO where the smaller temperature activation partially compensates the larger damage. In that case a security margin can be established giving a limit of V BS = −V DD /2 for design reliability.

Assembly of a capacitive acoustic transducer of the microelectromechanical type and package thereof

Abstract: A microelectromechanical-acoustic-transducer assembly has: a first die integrating a MEMS sensing structure having a membrane, which has a first surface in fluid communication with a front chamber and a second surface, opposite to the first surface, in fluid communication with a back chamber of the microelectromechanical acoustic transducer, is able to undergo deformation as a function of incident acoustic-pressure waves, and faces a rigid electrode so as to form a variable-capacitance capacitor; a second die, integrating an electronic reading circuit operatively coupled to the MEMS sensing structure and supplying an electrical output signal as a function of the capacitive variation; and a package, housing the first die and the second die and having a base substrate with external electrical contacts. The first and second dice are stacked in the package and directly connected together mechanically and electrically; the package delimits at least one of the front and back chambers.

Advances in 3D CMOS sequential integration

Abstract: For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 4A of the Equivalent Oxide Thickness is measured when a low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization.

Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit

Abstract: As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its nonvolatility and high write/read speed allow to power down completely the logic blocks in “idle” states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM technology are presented in this article. By using STMicroelectronics CMOS 90nm technology and a STT-MTJ spice model, some chip characteristic results as the programming latency and power have been calculated and simulated to demonstrate the expected performance of STT-MRAM based FPGA logic circuits.

Onsite matrix elements of the tight-binding Hamiltonian of a strained crystal: Application to silicon, germanium, and their alloys

Abstract: We discuss a model for the onsite matrix elements of the $s{p}^{3}{d}^{5}{s}^{\ensuremath{\ast}}$ tight-binding Hamiltonian of a strained diamond or zinc-blende crystal or nanostructure. This model features onsite, off-diagonal couplings among the $s$, $p$, and $d$ orbitals and is able to reproduce the effects of arbitrary strains on the band energies and effective masses in the full Brillouin zone. It introduces only a few additional parameters and is free from any ambiguities that might arise from the definition of the macroscopic strains as a function of the atomic positions. We apply this model to silicon, germanium, and their alloys as an illustration. In particular, we make a detailed comparison of tight-binding and ab initio data on strained Si, Ge, and SiGe.

0.13 $\mu$ m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications

Abstract: This paper presents a complete 0.13 μm SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 fF/μm2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques

Abstract: Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled processes. Particularly, all-digital PLLs are being considered for RF frequency synthesis. However, they suffer from intrinsic deficiencies making them inferior to traditional analog solutions. The investigation in this paper shows that in-band output spurs, the major shortcoming of wideband divider-less ADPLLs with respect to analog fractional PLLs, are intrinsic and due to the finite resolution of the time-to-digital converter (TDC), even assuming perfect quantization and linearity. Moreover, even if the conceptual spur level is arbitrarily reduced by increasing the TDC resolution, TDC nonlinearities can cause a significant spur re-growth. This paper proposes two techniques to reduce the gap between all-digital and analog implementations of wideband fractional PLLs. These techniques have been applied to a 3 GHz ADPLL, whose bandwidth is programmable from 300 kHz to 1.8 MHz, operating from a 25 MHz reference signal. The test chip features more than 10 dB of worst in-band spur reduction when both corrections are active, for a worst-case in-band spur of -45 dBc at a bandwidth of 1.8 MHz and an in-band noise floor of -101 dBc/Hz. The chip core occupies 0.4 mm2 in 65 nm CMOS technology, and consumes less than 10 mW from a 1.2 V supply.

Multiple-channel transmission over a single-wire bus

Abstract: Apparatus and methods are described that enable concurrent transmission of multiple data signals including clock, synchronization, and power over a single-wire bus between a master device and one or more slave devices. A first transmission channel from the master device to the slave device may modulate the width of periodic pulses between a first voltage level and a second voltage level with respect to a reference potential. A second transmission channel may modulate the amplitude of at least one of the first and second voltage levels to at least one third voltage level. Concurrent communications between a master device and one or more slave devices over a single-wire bus can be achieved.

A GHz spintronic-based RF oscillator

Abstract: A nano-sized oscillator for RF applications is presented which is based on two spintronic effects, the tunneling magnetoresistance (TMR) and the spin momentum transfer torque. The oscillation frequency is several GHz and can be tuned by both a DC bias current and an external DC magnetic field. High compactness, high tunability and full compatibility with standard CMOS process make this spin torque nano-oscillator (STNO) a promising candidate for future RF transceivers. The main issues to be addressed are spectral purity and output power. First measurements on a hybrid built connecting the STNO to a dedicated wideband amplifier show that today's performance in terms of power is close to but not yet compatible with telecommunication standard requirements. Using time domain analysis we show that frequency fluctuations are an issue for spectral purity. Frequency synthesis concepts based on STNOs are also discussed.

Nanoscale CMOS Transceiver Design in the 90–170-GHz Range

Abstract: This paper reviews recent research conducted at the University of Toronto on the development of CMOS transceivers aimed at operation in the 90-170-GHz range. Unique nanoscale CMOS issues related to millimeter-wave circuit design in the 65-nm node and beyond are addressed with an emphasis on transistor and top-level layout issues, low-voltage circuit topologies, and design flow. A Doppler transceiver and two receivers fabricated in a 65-nm GPLP CMOS technology are described, along with a single pole, double throw antenna switch with better than 5-dB insertion loss and 25-dB isolation in the entire 110-170-GHz band. The first receiver has an IQ architecture with a fundamental frequency voltage-controlled oscillator, and is intended for wideband passive imaging applications at 100 GHz. The measured noise figure and downconversion gain are 7-8 and 10.5 dB, respectively, while the 3-dB bandwidth extends from 85 to 100 GHz. The second receiver has double-sideband architecture, operates in the 135-145-GHz range (the highest for CMOS receivers), and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer, and a dipole antenna. The 90-94-GHz Doppler transceiver, the highest frequency reported to date in CMOS, is intended for the remote monitoring of respiratory functions. A Doppler shift of 30 Hz, produced by a slow-moving (4.8 cm/s) target located at a distance of 1 m, was measured with a transmitter output power of approximately + 2 dBm and a phase noise of -90 dBc/Hz at 1 MHz offset. The range correlation effect is demonstrated for the first time in CMOS by measuring the phase noise of the received baseband signal at 10-Hz offset, clearly indicating that 1/f noise has been canceled and it does not pose a problem in short-range applications, where neither a phase-locked loop nor a frequency divider are needed.

A low-noise single-photon detector implemented in a 130 nm CMOS imaging process

Abstract: We report on a new single-photon avalanche diode (SPAD) fabricated in a 130 nm CMOS imaging process. A novel circular structure combining shallow trench isolation (STI) and a passivation implant creates an effective guard ring against premature edge breakdown. Thanks to this guard ring, unprecedented levels of miniaturization may be achieved at no cost of added noise, decreased sensitivity, or timing resolution. The detector, integrated along with quenching and readout electronics, was fully characterized. A second batch of detectors with decreased n-well doping was fabricated, thus reducing the dark count rate (DCR) by several orders of magnitude. To the best of our knowledge, the DCR per unit area achieved in these devices is the lowest ever reported in deep sub-micron CMOS SPADs. Optical measurements show the effectiveness of the guard ring and the high degree of electric field planarity across the sensitive region of the detector. With a photon detection probability (PDP) of up to 36% and a timing jitter of 125 ps at full-width-half-maximum, this SPAD is well-suited for applications such as 3D imaging, fluorescence lifetime imaging, and biophotonics.

A low-noise single-photon detector implemented in a 130 nm CMOS imaging process

Abstract: We report on a new single-photon avalanche diode (SPAD) fabricated in a 130 nm CMOS imaging process. A novel circular structure combining shallow trench isolation (STI) and a passivation implant creates an effective guard ring against premature edge breakdown. Thanks to this guard ring, unprecedented levels of miniaturization may be achieved at no cost of added noise, decreased sensitivity, or timing resolution. The detector, integrated along with quenching and readout electronics, was fully characterized. A second batch of detectors with decreased n-well doping was fabricated, thus reducing the dark count rate (DCR) by several orders of magnitude. To the best of our knowledge, the DCR per unit area achieved in these devices is the lowest ever reported in deep sub-micron CMOS SPADs. Optical measurements show the effectiveness of the guard ring and the high degree of electric field planarity across the sensitive region of the detector. With a photon detection probability (PDP) of up to 36% and a timing jitter of 125 ps at full-width-half-maximum, this SPAD is well-suited for applications such as 3D imaging, fluorescence lifetime imaging, and biophotonics.

A 32x32-pixel array with in-pixel photon counting and arrival time measurement in the analog domain

Abstract: A Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion is implemented in a 130-nm CMOS imaging technology. The proposed module is conceived for Single-Photon Avalanche Diode imagers and can operate both as a TAC or as an analog counter, thus allowing both time-correlated or time-uncorrelated imaging operation. A single-ramp, 8-bit ADC with two memory banks to allow high-speed, time-interleaved operation is also included within each module. A 32x32-TACs array has been fabricated with a 50-µm pitch in order prove the highly parallel operation and to test uniformity and power consumption issues. The measured time resolution (LSB) is of 160 ps on a 20-ns time range with a uniformity across the array within ±2LSBs, while DNL and INL are 0.7LSB and 1.9LSB respectively. The average power consumption is below 300µW/pixel when running at 500k measurements per second.

Current sharing in three-phase LLC interleaved resonant converter

Abstract: In this paper, a novel approach for multi-phase interleaved LLC resonant converter is presented. The proposed solution, based on the use of three LLC modules with star connection of transformer primary windings, allows a drastic reduction of the output current ripple and consequently of the output filter capacitor size. Differently from other multi-phase solutions, that are greatly susceptible to resonant components' tolerance causing current imbalance, the proposed topology exhibits an inherent current sharing capability. Moreover, a closed-loop phase-shift control is introduced to additionally compensate for current mismatch and completely balance the current supplied by each module. The benefit of such solution on the reduction of output current ripple and the phase-shift control interaction and effect on load-step variations are also investigated. Measurements on a prototype are added to simulations as validation of the assertions and proposals.

System and method for sensing biometric and non-biometric smart card devices

Abstract: A system of detecting biometric and non-biometric, standard smart card devices includes a smart card host and smart card device reader, which is operable for receiving an Answer to Reset signal and determining whether the smart card device comprises a biometric or non-biometric, standard smart card device. If a biometric smart card device is detected, the smart card reader is operable for applying power used for standard smart card device operation to a first contact and applying power used by a biometric circuit to a second contact, and if a non-biometric, standard smart card device is detected, applying power only to the first contact.

Light absorption in silicon quantum dots embedded in silica

Abstract: The photon absorption in Si quantum dots (QDs) embedded in SiO2 has been systematically investigated by varying several parameters of the QD synthesis. Plasma-enhanced chemical vapor deposition (PECVD) or magnetron cosputtering (MS) have been used to deposit, upon quartz substrates, single layer, or multilayer structures of Si-rich-SiO2 (SRO) with different Si content (43–46 at. %). SRO samples have been annealed for 1 h in the 450–1250 °C range and characterized by optical absorption measurements, photoluminescence analysis, Rutherford backscattering spectrometry and x-ray Photoelectron Spectroscopy. After annealing up to 900 °C SRO films grown by MS show a higher absorption coefficient and a lower optical bandgap (∼2.0 eV) in comparison with that of PECVD samples, due to the lower density of Si–Si bonds and to the presence of nitrogen in PECVD materials. By increasing the Si content a reduction in the optical bandgap has been recorded, pointing out the role of Si–Si bonds density in the absorption proce...

Low Voltage Fault Attacks on the RSA Cryptosystem

Abstract: Fault injection attacks are a powerful tool to exploit implementative weaknesses of robust cryptographic algorithms. The faults induced during the computation of the cryptographic primitives allow to extract pieces of information about the secret parameters stored into the device using the erroneous results. Various fault induction techniques have been researched, both to make practical several theoretical fault models proposed in open literature and to outline new kinds of vulnerabilities. In this paper we describe a non-invasive fault model based on the effects of underfeeding the power supply of an ARM general purpose CPU. We describe the methodology followed to characterize the fault model on an ARM9 microprocessor and propose and mount attacks on implementations of the RSA primitives.

A 32×32 50ps resolution 10 bit time to digital converter array in 130nm CMOS for time correlated imaging

Abstract: We report the design and characterisation of a 32×32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50µm pitch TDC array exhibits a minimum time resolution of 50ps, with accuracy of ±0.5 LSB DNL and 2.4 LSB INL. Process, voltage and temperature compensation (PVT) is achieved by locking the array to a stable external clock. The resulting time correlated pixel array is a viable candidate for single photon counting (TCSPC) applications such as fluorescent lifetime imaging microscopy (FLIM), nuclear or 3D imaging and permits scaling to larger array formats.

Two-phase interleaved LLC resonant converter with current-controlled inductor

Abstract: Multi-phase interleaved converters represent interesting solutions in terms of reduced current rating of each module, reduction of input and output current ripples, and possibility of redundancy. However, when attempt to interleave resonant converters operating at the same switching frequency, the resonant components' tolerance can cause severe current unbalance between them. In this paper, a two-phase interleaved LLC resonant converter is proposed that employs a current-controlled inductor to adjust the resonance frequency of one module, thus compensating for component mismatch. Experimental results of a prototype rated at 24V-12A output are presented, confirming the theoretical forecasts.

Automatic Mode Matching in MEMS Vibrating Gyroscopes Using Extremum-Seeking Control

Abstract: In order to enhance the sensitivity and to reduce the readout circuit complexity of any angular velocity microsensor (vibrating gyroscope), it is crucial to reduce the frequency mismatch of its resonant modes of vibration. Achieving a good matching accuracy during fabrication is rather difficult because of tolerances and process variations that detrimentally affect the manufacturing precision. Moreover, even assuming to achieve a good frequency matching through fabrication or postfabrication calibration, it is very likely that parametric variations induced by the external environment during the normal operation of the device disrupt any initial tuning. For these reasons, in this paper, an alternative way to accomplish the frequency-matching condition is suggested, which exploits a real-time adjusting mechanism based on an automatic mode-matching control loop. In particular, this paper describes the details of an adaptive controller capable of automatically matching the resonant frequencies of the two main modes of vibration of a single-axis vibrating microgyroscope, under the provision that there is an underlying mechanism through which the frequency mismatch can be controlled by adjusting a suitable tunable parameter. The controller is designed by considering the requirement of reducing its complexity, so that it can be easily implemented on cheap sensors. Owing to a key observation that allows the recast of the frequency-matching problem as a maximization problem, the proposed mode-matching controller is actually designed as a standard perturbation-based extremum-seeking controller, which can be implemented by using few analog electronic components. The proposed solution has been tested on the LISY300AL yaw-rate microelectromechanical system gyroscope manufactured by STMicroelectronics, showing that a mode matching of nearly 1 Hz or less can be easily attained.

A parallel 32×32 time-to-digital converter array fabricated in a 130 nm imaging CMOS technology

Abstract: We report on the design and characterization of a 32 × 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at ± 0.4 and ±1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50µm in both directions and with a total TDC area of less than 2000µm2. The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).

High sensitivity protein assays on microarray silicon slides.

Abstract: In this work, we report on the improvement of microarray sensitivity provided by a crystalline silicon substrate coated with thermal silicon oxide functionalized by a polymeric coating. The improvement is intended for experimental procedures and instrumentations typically involved in microarray technology, such as fluorescence labeling and a confocal laser scanning apparatus. The optimized layer of thermally grown silicon oxide (SiO(2)) of a highly reproducible thickness, low roughness, and fluorescence background provides fluorescence intensification due to the constructive interference between the incident and reflected waves of the fluorescence radiation. The oxide surface is coated by a copolymer of N,N-dimethylacrylamide, N-acryloyloxysuccinimide, and 3-(trimethoxysilyl)propyl methacrylate, copoly(DMA-NAS-MAPS), which forms, by a simple and robust procedure, a functional nanometric film. The polymeric coating with a thickness that does not appreciably alter the optical properties of the silicon oxide confers to the slides optimal binding specificity leading to a high signal-to-noise ratio. The present work aims to demonstrate the great potential that exists by combining an optimized reflective substrate with a high performance surface chemistry. Moreover, the techniques chosen for both the substrate and surface chemistry are simple, inexpensive, and amenable to mass production. The present application highlights their potential use for diagnostic applications of real clinical relevance. The coated silicon slides, tested in protein and peptide microarrays for detection of specific antibodies, lead to a 5-10-fold enhancement of the fluorescence signals in comparison to glass slides.