Showing papers by "STMicroelectronics published in 2010"

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

Abstract: A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-?m 2.5-V standard I/O FETs in a 0.13-?m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.

Low-complexity decoding for non-binary LDPC codes in high order fields

Abstract: In this paper, we propose a new implementation of the Extended Min-Sum (EMS) decoder for non-binary LDPC codes. A particularity of the new algorithm is that it takes into accounts the memory problem of the non-binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our decoder is to truncate the vector messages of the decoder to a limited number nm of values in order to reduce the memory requirements. Using the truncated messages, we propose an efficient implementation of the EMS decoder which reduces the order of complexity to ?(nm log2 nm). This complexity starts to be reasonable enough to compete with binary decoders. The performance of the low complexity algorithm with proper compensation is quite good with respect to the important complexity reduction, which is shown both with a simulated density evolution approach and actual simulations.

Two independent components modeling for Negative Bias Temperature Instability

Abstract: Based on vast experimental dataset obtained from different technologies (pure or nitrided SiO 2 and HK), we suggest that Negative Bias Temperature Instability is made of two independent components, presenting different voltage and temperature acceleration factors as well as process dependences. The recoverable part, subject to fast transient effects, is shown to obey field-assisted LRME hole trapping/detrapping processes. The permanent part is shown to be made of an equal number of interface traps and positive fixed charges, as resulting from hydrogen transfer to oxygen bridge. This hydrogen transfer was shown for the firs time to be reversible allowing in-depth analysis of the microscopic mechanisms at play.

A Passive W-Band Imaging Receiver in 65-nm Bulk CMOS

Abstract: A passive imaging receiver operating in the W-band around 90 GHz has been realized in a digital 65-nm CMOS process. The circuit, occupying only 0.41 mm2, integrates an SPDT switch with 4.2 dB loss and 25 dB isolation, a five-stage telescopic cascode LNA with 27 dB gain at 90 GHz, and a W-band square-law detector, all consuming less than 33 mA from 1.2 V. A version of the receiver without the input SPDT switch has a peak responsivity of over 200 kV/W and a minimum NEP of less than 0.1 pW/ Hz. The full Dicke radiometer, which includes the input switch, achieves a responsivity of 90 kV/W and an NEP of 0.2 pW/ Hz. This work represents the first W-band passive imaging receiver to be implemented in standard CMOS with this level of integration.

A Resonant Microaccelerometer With High Sensitivity Operating in an Oscillating Circuit

Abstract: A new micromachined uniaxial silicon resonant accelerometer characterized by a high sensitivity and very small dimensions is presented. The device's working principle is based on the frequency variations of two resonating beams coupled to a proof mass. Under an external acceleration, the movement of the proof mass causes an axial load on the beams, generating opposite stiffness variations, which, in turn, result in a differential separation of their resonance frequencies. A high level of sensitivity is obtained, owing to an innovative and optimized geometrical design of the device that guarantees a great amplification of the axial loads. The acceleration measure is obtained, owing to a properly designed oscillating circuit. In agreement with the theoretical prediction, the experimental results show a sensitivity of 455 Hz/ ( g being the gravity acceleration) with a resonant frequency of about 58 kHz and a good linearity in the range of interest.

Electrical Behavior of Phase-Change Memory Cells Based on GeTe

Abstract: In this letter, we present a study on the electrical behavior of phase-change memories (PCMs) based on a GeTe active material. GeTe PCMs show, first, extremely rapid SET operation (yielding a gain of more than one decade in energy per bit with respect to standard GST PCMs), second, robust cycling, up to 1 × 105, with 30-ns SET and RESET stress time, and third, a better retention behavior at high temperature with respect to GST PCMs. These results, obtained on single cells, suggest GeTe as a promising alternative material to standard GST to improve PCM performance and reliability.

A 3×3, 5µm pitch, 3-transistor single photon avalanche diode array with integrated 11V bias generation in 90nm CMOS technology

Abstract: A 3×3 prototype image sensor array consisting of 2µm diameter CMOS avalanche photodiodes with 3-transistor NMOS pixel circuitry is integrated in a 90nm CMOS image sensor technology. The 5µm pixel pitch is the smallest achieved to date and is obtained with <1% crosstalk, 250Hz mean dark count rate (DCR) at 20C, 36% photon detection efficiency at 410nm (PDE) and 107ps FWHM jitter. The small pixel pitch makes it possible to recover the 12.5% fill factor by standard wafer-level microlenses. A 5-stage capacitive charge pump generates the 11V breakdown voltage from a standard 2.5V supply obviating external high voltage generation.

A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput

Abstract: A 90 nm 4 Mb embedded phase-change memory (PCM) is presented, demonstrating the feasibility of PCM integration with 3 masks overhead in a 6-ML standard CMOS process. Using a low-voltage NMOS transistor as a cell selector leads to a 0.29 ?m2 cell size. A 1.2 V low-voltage read operation achieves a 12 ns access time. The 3 mm2 macro features a random write throughput of 1 MB/s and a mode to increase write throughput to 4 MB/s.

Sponge-based pseudo-random number generators

Abstract: This paper proposes a new construction for the generation of pseudo-random numbers. The construction is based on sponge functions and is suitable for embedded security devices as it requires few resources. We propose a model for such generators and explain how to define one on top of a sponge function. The construction is a novel way to use a sponge function, and inputs and outputs blocks in a continuous fashion, allowing to interleave the feed of seeding material with the fetch of pseudo-random numbers without latency. We describe the consequences of the sponge indifferentiability results to this construction and study the resistance of the construction against generic state recovery attacks. Finally, we propose a concrete example based on a member of the KECCAK family with small width.

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

Abstract: The digital-intensive approach to frequency synthesis embodied by the ADPLL [1] has seen a flurry of recent activity [2–4] due to benefits in both performance (programmability, noise immunity) and integration (area reduction, easy porting) in nanoscale CMOS versus the traditional analog approach. However, the quantization of voltage and time—intrinsic to sampled-data systems—leads to problems with spurious tones and in-band phase noise the former of which has hitherto excluded the ADPLL from stringent wideband wireless applications. Low in-band phase noise requires a high-resolution TDC, whereas the dominant source of in-band spurious tones in an ADPLL is the TDC's nonlinearity, which is not directly coupled with TDC resolution. Although effective techniques to mitigate TDC nonlinearities have been proposed in [2,3], with worst-spur performance around −45dBc they are still far from analog state-of-the-art [6].

Apparatus and method for constant power offline LED driver

Abstract: A single-stage integrated circuit drives LED sources in a constant power mode to eliminate the need for LED current sensing, while reshaping the waveform of the inductor current near line zero crossing to achieve high power factor. The integrated circuit achieves substantially constant input power by maintaining a constant voltage at a power factor corrector controller through an input voltage feedforward system. Accordingly, the disclosed circuit provides a high power factor, high efficiency, simple, and cost-effective solution with substantially consistent input power for both isolated and non-isolated offline LED applications.

Through-package-via formation and metallization of glass interposers

Abstract: Interposer technology has evolved from ceramic to organic materials and most recently to silicon. Organic substrates exhibit poor dimensional stability, thus requiring large capture pads which make them unsuitable for very high I/Os with fine pitch interconnections. Therefore, there has been a trend to develop silicon interposers. Silicon interposers however, suffer in two ways; 1) they are expensive to process due to the need for electrical insulation around via walls, and 2) they are limited in size by the silicon wafer from which they originate. In this paper, glass is proposed as a superior alternative interposer technology to address the limitations of both silicon and organic interposers. The inherent electrical properties of glass, together with large area panel size availability, make it superior compared to organic and silicon-based interposers. Glass however, is not without its challenges. It suffers in two ways: 1) formation of vias at low cost, and 2) its lower thermal conductivity compared to silicon. This research explores glass as an interposer material, and addresses the above key challenges in through package via (TPV) formation and subsequent low cost and large area metallization to achieve very high I/Os at fine pitch.

Multi Fault Laser Attacks on Protected CRT-RSA

Abstract: Since the first publication of a successful practical two-fault attack on protected CRT-RSA surprisingly little attention was given by the research community to an ensuing new challenge. The reason for it seems to be two-fold. One is that generic higher order fault attacks are very difficult to model and thus finding robust countermeasures is also difficult. Another reason may be that the published experiment was carried out on an outdated 8 bit microcontroller and thus was not perceived as a serious threat to create a sense of urgency in addressing this new menace. In this paper we describe two-fault attacks on protected CRT-RSA implementations running on an advanced 32 bit ARM Cortex M3 core. To our knowledge, this is the first practical result of two fault laser attacks on a protected cryptographic application. Considering that laser attacks are much more accurate in targeting a particular variable, the significance of our result cannot be overlooked.

Soft-Switching Converter With HF Transformer for Grid-Connected Photovoltaic Systems

Abstract: In this paper, the design, realization, and performance evaluation of a single-phase 3-kW dc/ac power converter, using an active-bridge dc/dc converter and a full-bridge dc/ac, are introduced, presenting a novel solution on the industrial scenario for the considered application. Control algorithms, including the maximum power point tracking, paralleling to the grid, and converter switching signals, are digitally implemented on a standard microcontroller.

Integrated microelectromechanical gyroscope with improved driving structure

Abstract: An integrated MEMS gyroscope, is provided with: at least a first driving mass driven with a first driving movement along a first axis upon biasing of an assembly of driving electrodes, the first driving movement generating at least one sensing movement, in the presence of rotations of the integrated MEMS gyroscope; and at least a second driving mass driven with a second driving movement along a second axis, transverse to the first axis, the second driving movement generating at least a respective sensing movement, in the presence of rotations of the integrated MEMS gyroscope The integrated MEMS gyroscope is moreover provided with a first elastic coupling element, which elastically couples the first driving mass and the second driving mass in such a way as to couple the first driving movement to the second driving movement with a given ratio of movement

Tearing-proof method for writing data in a nonvolatile memory

Abstract: A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone.

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

Abstract: We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V T -variability performances are obtained (A VT =1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V DD =0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ SNM DD =0.7V. We also demonstrate ultra-low leakage ( G = 30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).

A 53-to-68GHz 18dBm power amplifier with an 8-way combiner in standard 65nm CMOS

Abstract: CMOS circuits operating up to 60GHz have been demonstrated to satisfy the market demand for high data rates and frequency bandwidths [1–6]. However, 60GHz products need an improvement in power performance as well as transistor reliability for large signal operation. Moreover, Class-A or Class-AB power amplifiers (PA) are mandatory to overcome the difficulty of the limited maximum available gain (MAG) at mm-Wave frequencies [1–6] and the high linearity required by the OFDM modulation used in the IEEE 802.15.3c wireless HD standard. That means a maximum drain-source voltage swing of twice the DC voltage, which introduces specific design or supply voltage in order to respect reliability constraints [1,7]. This paper describes a PA with 8 power-combined ways and cascode topology in a 7-metal-layer 65nm CMOS process which covers the full band for 60GHz wireless applications. The presented circuit operates at a standard supply of 1.2V or 1.8V, and achieves a saturated output power of 16.6dBm and 18.1dBm respectively. The measured output power is high for CMOS while insuring reliability for time-dependent dielectric breakdown (TDDB) and hot-carrier-injection (HCI) degradation.

Microelectromechanical gyroscope with position control driving and method for controlling a microelectromechanical gyroscope

Abstract: A MEMS gyroscope includes: a microstructure having a fixed structure, a driving mass, movable with respect to the fixed structure according to a driving axis, and a sensing mass, mechanically coupled to the driving mass so as to be drawn in motion according to the driving axis and movable with respect to the driving mass according to a sensing axis, in response to rotations of the microstructure; and a driving device, for keeping the driving mass in oscillation with a driving frequency. The driving device includes a discrete-time sensing interface, for detecting a position of the driving mass with respect to the driving axis and a control stage for controlling the driving frequency on the basis of the position of the driving mass.

A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications

Abstract: This work shows a complete PLL that is integrated in standard industrial 65nm CMOS technology. This frequency synthesizer is fully compliant with IEEE 802.15.3c normalization [1–4]. This PLL delivers a quadrature LO signal around 20GHz and a differential LO signal around 40GHz and has 17.9% tuning range. The wide tuning range of 17.9% permits to cover the full IEEE 802.15.3c band with industrial margin. The phase noise is −100dBc/Hz at 1MHz offset and the total power dissipation is only 80mW including the output buffers and amplifiers. Short-range wireless multi-Gb/sec communication systems use the mm-wave band of 57GHz to 66GHz, according to the IEEE 802.15.3c normalization. The frequency synthesis is one of the key elements for these transceivers. Indeed, one must take into account the antagonist tradeoff between large band tuning range of the frequency synthesizer and phase noise performance. In transceivers using super-heterodyne architecture with double conversion, the frequency synthesizer signal fLO can be equal to 2fRF /3 and fRF /3. In this case, to cover the four channels of the IEEE 802.15.3c normalization, the frequency synthesizer has to deliver a first local oscillator (LO) signal between 19.44GHz and 21.6GHz and a second LO signal between 38.88GHz and 43.2GHz, respectively. This architecture offers a good trade off between the required large frequency tuning range (≫15%) and low phase noise (≪−95dBc/Hz).

Capacitive -inductive touch screen

Abstract: A touch screen uses a combination of capacitive sensing and inductive sensing applied to the same sensor pattern. A capacitive sensor uses the electric field formed by the columns and rows of the sensor matrix. An inductive sensor uses the magnetic field formed by current flowing in column and row lines to induce an inductive pen. Using the same sensor lines, the magnetic field created by the oscillating inductive pen is detected. Both methods require no moving elements in the sensor and it is possible to combine both method of detections in the same sensor pattern. Using switch matrices, the sensor lines are operated in an open loop fashion for the capacitive detection mode, and are operated in a closed loop fashion for the inductive detection mode.

Dual accelerometer detector for clamshell devices

Abstract: A clamshell device having a dual accelerometer detector includes a first keyboard portion including a first accelerometer, a second display portion including a second accelerometer, a hinge for coupling the first portion to the second portion, and circuitry coupled to the first and second accelerometers for providing an output signal in response to the position of the first and second portions of the clamshell device. The output signal is provided to indicate a shutdown or standby mode, tablet operation mode, a partially shut or power savings mode, a normal operating mode, or an unsafe operating mode.

A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI

Abstract: A 60 GHz wideband power amplifier (PA) is fabricated in a standard CMOS SOI 65 nm process. The PA is based on two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high-resistivity SOI substrate (3 kΩ · cm). The PA measurements are carried out for supply voltages VDD going from 1.2 V to 2.6 V and achieve a saturation power of 10 dBm to 16.5 dBm respectively. The peak power-added efficiency (PAE) is higher than 20% for all applied VDD values.

Next generation eWLB (embedded wafer level BGA) packaging

Abstract: Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. “Fan-in” (FI)-WLP typically has a limitation to be less than 6x6mm in order to pass board level reliability requirements such as drop test and temperature cycle due to the mismatch of Si material properties to the PCB. However, the “Fan-out” (FO)-WLP, has been developed and introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. The most prominent type of FO-WLP is the eWLB technology (embedded Wafer Level Ball Grid Array). Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in next generation eWLB technologies including multi-RDL, thin eWLB and extra large eWLB as well as double-side with vertical interconnection. These key technologies of next generation eWLB enable 3D eWLB applications such as SoW (SiP on Wafer) and 3D SiP. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. The process flow of next generation eWLB fabrication, assembly and packaging challenges will be discussed. This paper will also present some of the achievements in package reliability, mechanical characterization and performance.

The Loudness War: Background, Speculation, and Recommendations

Abstract: There is growing concern that the quality of commercially distributed music is deteriorating as a result of mixing and mastering practices used in the so-called “loudness war.” Due to the belief that “louder is better,” dynamics compression is used to squeeze more and more loudness into the recordings. This paper reviews the history of the loudness war and explores some of its possible consequences, including aesthetic concerns and listening fatigue. Next, the loudness war is analyzed in terms of game theory. Evidence is presented to question the assumption that loudness is significantly correlated to listener preference and sales rankings. The paper concludes with practical recommendations for de-escalating the loudness war.

An Efficient Architecture for 3-D Discrete Wavelet Transform

Abstract: This paper presents an architecture of the lifting-based running 3-D discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. The proposed design is one of the first lifting based complete 3-D-DWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting signal flow graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput compared to those of earlier reported works. The proposed architecture has been successfully implemented on Xilinx Virtex-IV series field-programmable gate array, offering a speed of 321 MHz, making it suitable for real-time compression even with large frame dimensions. Moreover, the architecture is fully scalable beyond the present coherent Daubechies filterbank (9, 7).

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

Abstract: We present UTBB devices with a gate length (L G ) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V bb ) enables V t modulation of more than 125mV with a V bb of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V t and power management applications. We explore the impact of GP, BOX thickness and V bb on local V t variability for the first time. Excellent A Vt of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I g ) and lower external resistance (R ext ), thanks to a thicker inversion gate dielectric (T inv ) and body (T si ) thickness.

Countermeasures against fault attacks on software implemented AES: effectiveness and cost

Abstract: In this paper we present software countermeasures specifically designed to counteract fault injection attacks during the execution of a software implementation of a cryptographic algorithm and analyze the efficiency of these countermeasures We propose two approaches based on the insertion of redundant computations and checks, which in their general form are suitable for any cryptographic algorithm In particular, we focus on selective instruction duplication to detect single errors, instruction triplication to support error correction, and parity checking to detect corruption of a stored value We developed a framework to automatically add the desired countermeasure, and we support the possibility to apply the selected redundancy to either all the instructions of the cryptographic routine or restrict it to the most sensitive ones, such as table lookups and key fetching Considering an ARM processor as a target platform and AES as a target algorithm, we evaluate the overhead of the proposed countermeasures while keeping the robustness of the implementation high enough to thwart most or all of the known fault attacks Experimental results show that in the considered architecture, the solution with the smallest overhead is per-instruction selective doubling and checking, and that the instruction triplication scheme is a viable alternative if very high levels of injected fault resistance are required