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Showing papers by "STMicroelectronics published in 2012"


Proceedings ArticleDOI
12 Jun 2012
TL;DR: This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology, to show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values.
Abstract: For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ∼14Mb SRAM cells is demonstrated, allowing to measure for the first time Vmin of SRAM arrays.

392 citations


Proceedings ArticleDOI
10 May 2012
TL;DR: This work designed and implemented a receiver-driven adaptation algorithm for adaptive streaming that does not rely on cross-layer information or server assistance and integrated the algorithm with a prototype implementation of a streaming client based on the MPEG DASH (Dynamic Adaptive Streaming over HTTP) standard.
Abstract: Internet video makes up a significant part of the Internet traffic and its fraction is constantly growing. In order to guarantee best user experience throughout different network access technologies with dynamically varying network conditions, it is fundamental to adopt technologies enabling a proper delivery of the media content. One of such technologies is adaptive streaming. It allows to dynamically adapt the bit-rate of the stream to varying network conditions. There are various approaches to adaptive streaming. In our work, we focus on the receiver-driven approach where the media file is subdivided into segments, each of the segments is provided at multiple bit-rates, and the task of the client is to select the appropriate bit-rate for each of the segments. With this approach, the challenges are (i) to properly estimate the dynamics of the available network throughput, (ii) to control the filling level of the client buffer in order to avoid underflows resulting in playback interruptions, (iii) to maximize the quality of the stream, while avoiding unnecessary quality fluctuations, and, finally, (iv) to minimize the delay between the user's request and the start of the playback. During our work, we designed and implemented a receiver-driven adaptation algorithm for adaptive streaming that does not rely on cross-layer information or server assistance. We integrated the algorithm with a prototype implementation of a streaming client based on the MPEG DASH (Dynamic Adaptive Streaming over HTTP) standard. We evaluated the implemented prototype in real-world scenarios and found that it performes remarkably well even under challenging network conditions. Further, it exhibits stable and fair operation if a common link is shared among multiple clients.

253 citations


Journal ArticleDOI
TL;DR: This paper classifies firstly all the possible failures of STT-MRAM into “soft errors” and “hard errors’, and analyzes their impact on the memory reliability, and can find some efficient design solutions to address respectively these two types of errors and improve the reliability of STTs.

207 citations


Proceedings ArticleDOI
03 Jun 2012
TL;DR: P2012 is an area- and power-efficient many-core computing accelerator based on multiple globally asynchronous, locally synchronous processor clusters, and a dedicated version of the OpenCV vision library is provided in the P2012 SW Development Kit to enable visual analytics acceleration.
Abstract: P2012 is an area- and power-efficient many-core computing accelerator based on multiple globally asynchronous, locally synchronous processor clusters. Each cluster features up to 16 processors with independent instruction streams sharing a multi-banked one-cycle access L1 data memory, a multi-channel DMA engine and specialized hardware for synchronization and aggressive power management. P2012 is 3D stacking ready and can be customized to achieve extreme area and energy efficiency by adding domain-specific HW IPs to the cluster. The first P2012 SoC prototype in 28nm CMOS will sample in Q3, featuring four 16-processor clusters, a 1MB L2 memory and delivering 80GOPS (with 32 bit single precision floating point support) in 18mm2 with 2W power consumption (worst-case). P2012 can run standard OpenCL™ and proprietary Native Programming Model SW components to achieve the highest level of control on application-to-resource mapping. A dedicated version of the OpenCV vision library is provided in the P2012 SW Development Kit to enable visual analytics acceleration. This paper will discuss preliminary performance measurements of common feature extraction and tracking algorithms, parallelized on P2012, versus sequential execution on ARM CPUs.

204 citations


Proceedings ArticleDOI
12 Mar 2012
TL;DR: P2012 is an area- and power-efficient many-core computing fabric based on multiple globally asynchronous, locally synchronous (GALS) clusters supporting aggressive fine-grained power, reliability and variability management.
Abstract: P2012 is an area- and power-efficient many-core computing fabric based on multiple globally asynchronous, locally synchronous (GALS) clusters supporting aggressive fine-grained power, reliability and variability management. Clusters feature up to 16 processors and one control processor with independent instruction streams sharing a multi-banked L1 data memory, a multi-channel DMA engine, and specialized hardware for synchronization and scheduling. P2012 achieves extreme area and energy efficiency by supporting domain-specific acceleration at the processor and cluster level through the addition of dedicated HW IPs. P2012 can run standard OpenCL and OpenMP parallel codes well as proprietary Native Programming Model (NPM) SW components that provide the highest level of control on application-to-resource mapping. In Q3 2011 the P2012 SW Development Kit (SDK) has been made available to a community of RD it includes full OpenCL and NPM development environments. The first P2012 SoC prototype in 28nm CMOS will sample in Q4 2012, featuring four clusters and delivering 80GOPS (with single precision floating point support) in 15.2mm2 with 2W power consumption.

194 citations


Proceedings ArticleDOI
03 Apr 2012
TL;DR: A low-power 1kpixel terahertz camera chip fully compliant with an industrial 65nm ft/fmax=160GHz/200GHz CMOS process technology, designed to accommodate the optics for wide bandwidth in stand-off detection with a 40dBi Si-lens.
Abstract: Future imaging applications in the submillimeter-Wave range (300GHz to 3THz) require RF systems that can achieve high sensitivity and portability at low power consumption levels. In particular, CMOS process technologies are attractive due to their low price tag for industrial, surveillance, scientific, and medical applications. Recently, CMOS-based detectors have shown good sensitivity up to 1THz with NEPs on the order of 66pW/√(Hz) at 1THz [1]. However, CMOS terahertz imagers developed thus far have only operated single detectors based on lock-in measurement techniques to acquire raster-scanned images with frame rates on the order of minutes [2]. To address these impediments, we present a low-power 1kpixel terahertz camera chip fully compliant with an industrial 65nm f t /f max =160GHz/200GHz CMOS process technology. The active-pixel circuit topology is designed to accommodate the optics for wide bandwidth (0.6 to 1THz) in stand-off detection with a 40dBi Si-lens. It includes row/col select and integrate-and-dump circuitry capable of capturing terahertz images with video frame rates up to 25fps at a power consumption of 2.5μW/pixel.

120 citations


Proceedings ArticleDOI
01 Dec 2012
TL;DR: A novel “STI-last” integration scheme is developed to improve cSiGe uniformity and enable ultra high performance PFET with narrow widths and modulates device Vt, thus providing an additional knob to enable multi-Vt while maintaining undoped channels for all devices.
Abstract: For the first time, we report high performance hybrid channel ETSOI CMOS by integrating strained SiGe-channel (cSiGe) PFET with Si-channel NFET at 22nm groundrules. We demonstrate a record high speed ring oscillator (fan-out = 3) with delay of 8.5 ps/stage and 11.2 ps/stage at V DD = 0.9V and V DD = 0.7V, respectively, outperforming state-of-the-art finFET results. A novel “STI-last” integration scheme is developed to improve cSiGe uniformity and enable ultra high performance PFET with narrow widths. Furthermore, cSiGe modulates device V t , thus providing an additional knob to enable multi-V t while maintaining undoped channels for all devices.

91 citations


Journal ArticleDOI
TL;DR: In this paper, all-solid-state Li/LiPONB/Si cells were prepared using physical vapor deposition (PVD) techniques, and the cycle life and the coulombic efficiency were found to be excellent in these solid-state cells with almost no loss during 1500 cycles.
Abstract: All solid-state thin-film lithium microbatteries are a promising component able to fulfill most of the specific requirements to power autonomous microsystems. Nevertheless, metallic lithium, which is commonly used as the negative electrode in microbatteries, has a very low melting temperature (Tm = 181 °C) that appears to be incompatible with the solder-reflow operation (maximum temperature Tmax ≈ 260 °C) usually used to connect electronic components. Silicon is a promising candidate to replace lithium in solder-reflowable lithium-ion cells due to its high volumetric capacity (834 μAh cm−2 μm−1 for Li15Si4) and its ability to reversibly insert lithium at a low potential. Nevertheless, it suffers from a large volumetric expansion during lithium insertion (280%), which is partly responsible for a rapid capacity fading when cycled in liquid electrolyte. In this study, all-solid-state Li/LiPONB/Si cells are prepared using physical vapor deposition (PVD) techniques. The cycle life and the coulombic efficiency are found to be excellent in these solid-state cells with almost no loss during 1500 cycles. Despite the large volume expansion due to lithium insertion confirmed by scanning electron microscopy, no evidence of cracks is found in the film or at the electrode/electrolyte interface, even after 1500 cycles.

78 citations


Proceedings ArticleDOI
01 Dec 2012
TL;DR: It is demonstrated in 20nm ground rules that Vt is able to tune by more than 400mV, that transistor performance can be boosted by up to 30% and that Ioff can be controlled over 3 decades by allowing more than VDD/2 to be applied on the back gate.
Abstract: We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground rules that we are able to tune V t by more than 400mV, that transistor performance can be boosted by up to 30% and that I off can be controlled over 3 decades by allowing more than V DD /2 to be applied on the back gate.

75 citations


Journal ArticleDOI
TL;DR: In this article, the effects of the precursor composition and the nature of the additional surfactants on the structure and stability of low-polydispersity copper nanoparticles are characterized by TEM and UV-Vis analysis.
Abstract: Low-polydispersity copper nanoparticles (NPs) are prepared through hydrogenolysis of various organometallic copper precursors in an organic medium at moderate temperature. The effects of the precursor composition and the nature of the additional surfactants on the structure and stability of NPs are characterized by TEM and UV-Vis analysis. The improved air stability of copper NPs originating from amidinate copper and stabilized by an alkylamine compound (hexadecylamine) is evidenced and compared with the effect of a long chain carboxylic acid (oleic acid).

69 citations


Journal ArticleDOI
TL;DR: In this article, the effect of an electrolyte additive, the vinylene carbonate (VC), on electrochemical performances was investigated on sputtered silicon thin films which constitute a simple system (avoiding the use of binders or any conducting additive material).

Patent
14 Sep 2012
TL;DR: In this article, an integrated microelectromechanical structure is provided with a driving mass, anchored to a substrate via elastic anchorage elements and designed to be actuated in a plane with the driving movement; and a first sensing mass and a second sensing mass, suspended within, and coupled to, the driving mass via respective elastic supporting elements so as to be fixed with respect to the angular velocity.
Abstract: An integrated microelectromechanical structure is provided with a driving mass, anchored to a substrate via elastic anchorage elements and designed to be actuated in a plane with a driving movement; and a first sensing mass and a second sensing mass, suspended within, and coupled to, the driving mass via respective elastic supporting elements so as to be fixed with respect thereto in said driving movement and to perform a respective detection movement in response to an angular velocity. In particular, the first and the second sensing masses are connected together via elastic coupling elements, configured to couple their modes of vibration.

Patent
21 Dec 2012
TL;DR: In this paper, an insulating layer between the semiconducting channel (fin) and the substrate was proposed to prevent channel-to-substrate leakage in a FinFET device.
Abstract: Channel-to-substrate leakage in a FinFET device can be prevented by inserting an insulating layer between the semiconducting channel (fin) and the substrate Similarly, source/drain-to-substrate leakage in a FinFET device can be prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate The insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage If an array of semiconducting fins is made up of a multi-layer stack, the bottom material can be removed thus yielding a fin array that is suspended above the silicon surface A resulting gap underneath the remaining top fin material can then be filled in with oxide to better support the fins and to isolate the array of fins from the substrate The resulting FinFET device is fully substrate-isolated in both the gate region and the source/drain regions

Journal ArticleDOI
TL;DR: In this article, the impact of the morphology of p-type implanted SiC, annealed under different conditions, on the properties of Ti/Al contacts and the influence of different annealing conditions on the channel mobility in 4H-SiC MOSFETs was also addressed.

Journal ArticleDOI
TL;DR: In this article, an analysis of low-frequency noise in n-channel and p-channel MOSFETs, with high-k gate stack and channel length varying from 1.8μm down to 26.4nm, has been carried out.
Abstract: Extensive investigation of the low-frequency noise in n-channel and p-channel MOSFETs, with high-k gate stack and channel length varying from 1.8 μm down to 26.4 nm, has been carried out. The results demonstrate that the carrier number fluctuation with correlated mobility fluctuations describes accurately and continuously the 1/f noise for all operation regions, i.e. from weak to strong inversion and from linear to saturation. It has been found that the product of the Coulomb scattering coefficient and the effective carrier mobility α sc μ eff is constant over a wide range of the drain current due to the interplay of the Coulomb scattering coefficient αsc and the effective carrier mobility μeff variations. In addition, a non-linear increase in the square root of the input gate voltage noise with the gate voltage overdrive was observed explained by the surface roughness scattering. The overall results lead to an analytical expression for the 1/f noise model, enabling to predict the noise level of a transistor with any channel dimensions using its transfer characteristic. This finding makes the noise model suitable for circuit simulation tools.

Journal ArticleDOI
TL;DR: In this article, the dark current behavior of the pixels forming the Si photomultiplier as a function of the applied overvoltage and operation temperature is studied, and the data are modeled by assuming that dark current is caused by current pulses triggered by events of diffusion of single minority carriers injected from the peripheral boundaries of the active area depletion layer and by thermal emission of carriers from Shockley-Read-Hall defects in the active surface depletion layer.
Abstract: The dark current behavior of the pixels forming the Si photomultiplier as a function of the applied overvoltage and operation temperature is studied. The data are modeled by assuming that dark current is caused by current pulses triggered by events of diffusion of single minority carriers injected from the peripheral boundaries of the active area depletion layer and by thermal emission of carriers from Shockley–Read–Hall defects in the active area depletion layer.

Journal ArticleDOI
TL;DR: A novel class of organometallic molecules, 6-3,6-bis(1-ethylferrocen)-9H-carbazol-9-yl-6-hexan-1-thiols, which are engineered to satisfy all such crucial requirements at once, as confirmed by electrochemistry and scanning tunneling microscopy measurements, and first principles density functional calculations.
Abstract: Quantum-dot Cellular Automata (QCA) exploit quantum confinement, tunneling and electrostatic interaction for transistorless digital computing. Implementation at the molecular scale requires carefully tailored units which must obey several structural and functional constraints, ranging from the capability to confine charge efficiently on different ‘quantum-dot centers’—in order to sharply encode the Boolean states—up to the possibility of having their state blanked out upon application of an external signal. In addition, the molecular units must preserve their geometry in the solid state, to interact electrostatically in a controlled way. Here, we present a novel class of organometallic molecules, 6-3,6-bis(1-ethylferrocen)-9H-carbazol-9-yl-6-hexan-1-thiols, which are engineered to satisfy all such crucial requirements at once, as confirmed by electrochemistry and scanning tunneling microscopy measurements, and first principles density functional calculations.

Patent
08 Mar 2012
TL;DR: In this article, an embodiment of a RF identification device is formed by a tag and by a reader, which is integrated in a single structure in completely monolithic form, where the antenna of the tag and the processing circuit are integrated in the single structure.
Abstract: An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.

Proceedings ArticleDOI
06 Mar 2012
TL;DR: In this paper, a Tri-Gate Nanowire (TGNW) FET with high-k/metal gate is studied as an alternative way to planar devices for the future CMOS technological nodes (14nm and beyond).
Abstract: In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.

Patent
18 Dec 2012
TL;DR: In this article, a dual mode capacitance switching circuit is proposed to switch between the mutual and self capacitance sensing modes of a capacitance-to-voltage (C2V) converter with an amplifier and an integration capacitance coupled between an output and an inverting input.
Abstract: Capacitance sensing circuits and methods are provided. A dual mode capacitance sensing circuit includes a capacitance-to-voltage converter having an amplifier and an integration capacitance coupled between an output and an inverting input of the amplifier, and a dual mode switching circuit responsive to mutual mode control signals for a controlling signal supplied from a capacitive touch matrix to the capacitance-to-voltage converter in a mutual capacitance sensing mode and responsive to self mode control signals for controlling signals supplied from the capacitive touch matrix to the capacitance-to-voltage converter in a self capacitance sensing mode, wherein the capacitance sensing circuit is configurable for operation in the mutual capacitance sensing mode or the self capacitance sensing mode.

Proceedings Article
12 Nov 2012
TL;DR: In this paper, the authors proposed a new method to reduce the number of intra-prediction modes in Rough Mode Decision (RMD) process by using direction information of the co-located neighboring block of previous frame along with neighboring blocks of current frame to speed up intra mode decision.
Abstract: Today, H.264/AVC coding standards is widely used for efficient coding of video signals. But to cope with resolutions higher than high definition (HD) more efficient coding is needed. A successor to the H.264/AVC codec is now developed by JCT-VC standard called High Efficiency Video Coding (HEVC). To improve the coding efficiency of intra frame, up to 35 intra prediction modes are defined in HEVC. A list of candidates for Rate Distortion Optimization (RDO) is formed by considering all the 35 intra prediction modes using a process called Rough Mode Decision (RMD). We note that each intra-mode processing in RMD is quite compute-intensive. To alleviate this computation load, this paper proposes a new method to reduce the number of intra-prediction modes in RMD process. This method plans to use direction information of the co-located neighboring block of previous frame along with neighboring blocks of current frame to speed up intra mode decision. In this proposed method, a candidate list is created which includes only 17 modes instead of 35 modes used in reference software. Experimental results show that this method selects 35%, 23% and 36% intra mode from candidate list for main profile Class A, B and E cases on an average as compared to the default encoding scheme in HM 6.0 with almost the same coding efficiency. This reduces complexity of rough mode decision algorithm.

Proceedings ArticleDOI
03 Apr 2012
TL;DR: A major limitation of this approach is the restrictively low photon count limit of 1-to-5% of the excitation rate, which is necessary in order to avoid distortion due to photon `pile-up' caused by both long detector dead-time and the inability of the TDC hardware to process more than one event per excitation period.
Abstract: Time-correlated single photon counting (TCSPC) is a technique whereby low-light signals are recorded with picosecond timing resolution relative to a synchronized optical impulse excitation, in order to extract the characteristic fluorescence decay constant, or lifetime [1]. Typical TCSPC apparatus includes a pulsed optical source, a discrete detector such as an avalanche photodiode (APD) or photomultiplier tube (PMT), external time-to-digital conversion (TDC) hardware and a PC to compute the decay constant, resulting in a bulky, expensive and power-hungry acquisition system. A major limitation of this approach is the restrictively low photon count limit of 1-to-5% of the excitation rate, which is necessary in order to avoid distortion due to photon ‘pile-up’ caused by both long detector dead-time and the inability of the TDC hardware to process more than one event per excitation period. As such, promising applications of TCSPC including cell cytometry, confocal microscopy, high throughput screening (HTS), and functional near infrared spectroscopy (fNIRS) are severely limited by peak acquisition rates of 1MHz. Although 100MHz has been achieved [2], the approach used is restricted to fluorescent dyes with lifetimes less than 2ns. Recent advances in single-photon avalanche diodes (SPADs) and on-chip TDCs manufactured in standard CMOS processes have enabled TCSPC measurements to be performed by an imaging array [3]; however such devices produce data at over 25Gb/s, have low fill factors of ∼2% and pixel update rates are limited. Time-gated lifetime sensing significantly reduces the data bandwidth and processing time [4,5], but is photon inefficient and still limited by pile-up.

Journal ArticleDOI
TL;DR: A theoretical framework about interface states creation rate from Si H bond breaking at the Si/SiO 2 interface during Hot Carrier (HC) stress is presented, which allows physical modeling of the reliability of MOS transistors, for different HC stress conditions.

Journal ArticleDOI
TL;DR: In this article, the effect of a solder-reflow type thermal treatment on the composition, local structure and electrical performances of the most used solid electrolyte, a lithium phosphorus oxynitride (LiPON), was investigated.

Proceedings ArticleDOI
08 Jul 2012
TL;DR: In this article, the authors present 60 GHz integrated antennas in an innovative low cost High Density Interconnect (HDI) organic technology demonstrating promising high gain antenna solution (> 7 dBi).
Abstract: During past years, various research teams have been implied in the development of 60 GHz chipset solutions, using both BiCMOS and advanced CMOS technologies. But for the 60 GHz market to flourish not only low cost RFICs are required, low cost antennas and packages are also key points. So far, HTCC technology has been seen as the chosen one when targeting millimeter wave (MMW) applications. But since 60 GHz applications are targeting large volume consumer applications, the pressure on the cost of the packaging will become higher and it is highly desirable to explore alternative lower cost solutions than HTCC. In this paper, we present 60GHz integrated antennas in an innovative low cost High Density Interconnect (HDI) organic technology demonstrating promising high-gain antenna solution (> 7 dBi).

Book ChapterDOI
28 Nov 2012
TL;DR: In this paper, the authors implemented different algorithms on an ATMEL AVR ATtiny45 8-bit microcontroller, and provided their performance evaluation, with the goal of minimizing the code size and memory utilization, and evaluated using a common interface.
Abstract: The pervasive diffusion of electronic devices in security and privacy sensitive applications has boosted research in cryptography. In this context, the study of lightweight algorithms has been a very active direction over the last years. In general, symmetric cryptographic primitives are good candidates for low-cost implementations. For example, several previous works have investigated the performance of block ciphers on various platforms. Motivated by the recent SHA3 competition, this paper extends these studies to another family of cryptographic primitives, namely hash functions. We implemented different algorithms on an ATMEL AVR ATtiny45 8-bit microcontroller, and provide their performance evaluation. All the implementations were carried out with the goal of minimizing the code size and memory utilization, and are evaluated using a common interface. As part of our contribution, we make all the corresponding source codes available on a web page, under an open-source license. We hope that this paper provides a good basis for researchers and embedded system designers who need to include more and more functionalities in next generation smart devices.

Proceedings ArticleDOI
03 Apr 2012
TL;DR: This work presents a batteryless CMOS RF transceiver for WSN nodes that includes a fully functional receiver for symmetrical RX/TX throughput and exploits narrowband active transmission to improve the uplink reading range without burdening the reader complexity.
Abstract: RF-powered transponders provide a low-cost and potentially free-of-maintenance solution for wireless sensor network (WSN) applications. By combining sensing functionalities and batteryless (RFID-like) wireless connectivity, these devices provide a viable option for all those scenarios in which node battery replacement is impractical because of either a huge number of deployed devices or inaccessible node placement. Extension of the reading range is a key design issue for RF-powered WSNs. When a backscattering-based passive RFID approach is adopted, the downlink reading range is limited by the power threshold of the input rectifier, whereas the uplink range is limited by the reader self-jamming. As increasingly efficient RF-to-DC power conversion schemes are being introduced, the uplink power budget will likely be the bottleneck of future passive RFID systems [1]. Replacing backscattering with an active transmission scheme can overcome such limitation. Several works have been reported so far following this approach. Asymmetric RF links with UWB uplink transmission have been proposed [2–4] with the aim of achieving both high data rates and low current consumption through very simple (crystal-less) circuit architectures at the sensor node side. However, adopting a UWB transmission approach considerably challenges the receiver section of the reader, thus potentially resulting in a net increase of the overall system complexity [5]. This is particularly critical in the case of mobile readers. Batteryless telemetry nodes with narrowband active transmission have also been demonstrated in [6] and [7]. Nevertheless, these circuits are not suitable for advanced communication functionalities (e.g., tag addressing, polling or control) due to the lack of a proper receiver section.

Journal ArticleDOI
TL;DR: The article contrasts two models of regimes in transition(s), the classical model of evolutionary niches and a second model based on ‘unlocking rules’, which support collective work on a structured set of emerging technologies.
Abstract: In a multi-level perspective, regimes can be clearly described as long as they remain stable. To understand how regimes and niches interact during transition, the article contrasts two models of regimes in transition(s). The classical model of evolutionary niches suggests misalignments between rules and competition between niches. Transition management, technological innovation systems and works on transition pathways suggest a second model based on "unlocking rules", which support collective work on a structured set of emerging technologies. The latter model is illustrated with a case study on the International Technology Roadmap for Semiconductors (ITRS).

Proceedings ArticleDOI
15 Apr 2012
TL;DR: In this article, a real-time Soft Error Rate (SER) characterization of more than 7 Gbit of SRAM circuits manufactured in 40 nm CMOS technology and subjected to natural radiation (atmospheric neutrons) is reported.
Abstract: This work reports the real-time Soft-Error Rate (SER) characterization of more than 7 Gbit of SRAM circuits manufactured in 40 nm CMOS technology and subjected to natural radiation (atmospheric neutrons). This experiment has been conducted since March 2011 at mountain altitude (2552 m of elevation) on the ASTEP Platform. The first experimental results, cumulated over more than 7,500 h of operation, are analyzed in terms of single bit upset, multiple cell upsets, physical bitmap and convergence of the SER. The comparison of the experimental data with Monte Carlo simulations and accelerated tests is finally reported and discussed.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, the authors present the superior performance of Ultra-Thin Box and Body (UTBB) technology for providing high speed at low voltage, and demonstrate on a full CPU Core implementation with UTBB a total power reduction of −30% and a +40% energy efficiency at identical speed with respect to bulk technology thanks to back side gate biasing efficiency.
Abstract: This paper presents the superior performance of UTBB (Ultra-Thin Box and Body) technology for providing high speed at low voltage. We evidence the transistor capability to sustain full forward-body-biasing solution thanks to a planar back-side gate scheme. Silicon measurements on low complexity circuits show that the dynamic power consumption can be reduced by 90% without any speed degradation by simply selecting the appropriate power supply and body bias couple (V dd ; V bb ). A simple switching energy efficiency model is then proposed allowing the (V dd ; V bb ) couple prediction reaching the minimum energy point. Finally, we demonstrate on a full CPU Core implementation with UTBB a total power reduction of −30% and a +40% energy efficiency at identical speed with respect to bulk technology thanks to back side gate biasing efficiency.