Showing papers by "STMicroelectronics published in 2017"

VUzzer: Application-aware Evolutionary Fuzzing.

Abstract: See, stats, and : https : / / www . researchgate . net / publication / 311886374 VUzzer : Application - aware Conference DOI : 10 . 14722 / ndss . 2017 . 23404 CITATIONS 0 READS 17 6 , including : Some : Systems Sanjay Vrije , Amsterdam , Netherlands 38 SEE Ashish International 1 SEE Cristiano VU 51 SEE Herbert VU 163 , 836 SEE All . The . All - text and , letting . Abstract—Fuzzing is an effective software testing technique to find bugs . Given the size and complexity of real - world applications , modern fuzzers tend to be either scalable , but not effective in exploring bugs that lie deeper in the execution , or capable of penetrating deeper in the application , but not scalable . In this paper , we present an application - aware evolutionary fuzzing strategy that does not require any prior knowledge of the application or input format . In order to maximize coverage and explore deeper paths , we leverage control - and data - flow features based on static and dynamic analysis to infer fundamental prop - erties of the application . This enables much faster generation of interesting inputs compared to an application - agnostic approach . We implement our fuzzing strategy in VUzzer and evaluate it on three different datasets : DARPA Grand Challenge binaries (CGC) , a set of real - world applications (binary input parsers) , and the recently released LAVA dataset . On all of these datasets , VUzzer yields significantly better results than state - of - the - art fuzzers , by quickly finding several existing and new bugs .

Hybrid indium phosphide-on-silicon nanolaser diode

Abstract: By exploiting one-dimensional photonic crystal nanocavities, an ultra-compact indium phosphide-on-silicon laser diode with low current threshold, high wall-plug efficiency and high integrability is demonstrated. The most-awaited convergence of microelectronics and photonics promises to bring about a revolution for on-chip data communications and processing1. Among all the optoelectronic devices to be developed, power-efficient nanolaser diodes able to be integrated densely with silicon photonics and electronics are essential to convert electrical data into the optical domain. Here, we report a demonstration of ultracompact laser diodes based on one-dimensional (1D) photonic crystal (PhC) nanocavities2,3,4 made in InP nanoribs heterogeneously integrated on a silicon-waveguide circuitry. The specific nanorib design enables an efficient electrical injection of carriers in the nanocavity without spoiling its optical properties. Room-temperature continuous-wave (CW) single-mode operation is obtained with a low current threshold of 100 µA. Laser emission at 1.56 µm in the silicon waveguides is obtained with wall-plug efficiencies greater than 10%. This result opens up exciting avenues for constructing optical networks at the submillimetre scale for on-chip interconnects and signal processing.

Comparison of the Device Lifetime in Wireless Networks for the Internet of Things

Abstract: This paper presents a comparison of the expected lifetime for Internet of Things (IoT) devices operating in several wireless networks: the IEEE 802.15.4/e, Bluetooth low energy (BLE), the IEEE 802.11 power saving mode, the IEEE 802.11ah, and in new emerging long-range technologies, such as LoRa and SIGFOX. To compare all technologies on an equal basis, we have developed an analyzer that computes the energy consumption for a given protocol based on the power required in a given state (Sleep, Idle, Tx, and Rx) and the duration of each state. We consider the case of an energy constrained node that uploads data to a sink, analyzing the physical (PHY) layer under medium access control (MAC) constraints, and assuming IPv6 traffic whenever possible. This paper considers the energy spent in retransmissions due to corrupted frames and collisions as well as the impact of imperfect clocks. The comparison shows that the BLE offers the best lifetime for all traffic intensities in its capacity range. LoRa achieves long lifetimes behind 802.15.4 and BLE for ultra low traffic intensity; SIGFOX only matches LoRa for very small data sizes. Moreover, considering the energy consumption due to retransmissions of lost data packets only decreases the lifetimes without changing their relative ranking. We believe that these comparisons will give all users of IoT technologies indications about the technology that best fits their needs from the energy consumption point of view. Our analyzer will also help IoT network designers to select the right MAC parameters to optimize the energy consumption for a given application.

14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems

Abstract: A booming number of computer vision, speech recognition, and signal processing applications, are increasingly benefiting from the use of deep convolutional neural networks (DCNN) stemming from the seminal work of Y. LeCun et al. [1] and others that led to winning the 2012 ImageNet Large Scale Visual Recognition Challenge with AlexNet [2], a DCNN significantly outperforming classical approaches for the first time. In order to deploy these technologies in mobile and wearable devices, hardware acceleration plays a critical role for real-time operation with very limited power consumption and with embedded memory overcoming the limitations of fully programmable solutions.

Printable stretchable interconnects

Abstract: This article presents recent progress and a comprehensive overview of the stretchable interconnects based on printable nanocomposites. The nanocomposites based inks for printed stretchable interconnects have been categorized according to the dispersed filler materials. They comprise of carbon-based and metal-based fillers. Benefits in terms of excellent electrical performance and elastic properties, make nanocomposites the ideal candidates for stretchable interconnect applications. The deeper analysis of nanocomposites based stretchable interconnects include the correlation between the size of fillers, percolation ratio, maximum electrical conductivity and mechanical elasticity. The key trends in the field have been highlighted using the curve fitting methods on the large data collected from literature. Furthermore, a wide variety of applications for stretchable interconnects are presented.

SiGe HBT Technology: Future Trends and TCAD-Based Roadmap

Abstract: A technology roadmap for the electrical performance of high-speed silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) is presented based on combining the results of various 1-D, 2-D, and 3-D technology computer-aided design (TCAD) simulation tools with geometry scalable compact modeling. The latter, including all known parasitic effects, enables the accurate determination of the figures of merit for both devices and selected benchmark circuits. The presented roadmap defines five major technology nodes with the maximum oscillation frequency of a typical high-frequency device structure as the main device design target under the constraints of various other parameters for generating the doping profiles and for defining the lateral scaling factors. An extensive and consistent set of technology and electrical parameters is provided along with the obtained scaling rules. The expected fabrication-related challenges and possible solutions for achieving the predicted performance are being discussed. It is hoped that the presented roadmap will be useful not only for foundries and equipment manufacturers but also for circuit and system designers enabling better predictions of the capability of SiGe–BiCMOS process technology for new millimeter-wave (mm-wave) and terahertz (THz) applications.

PCR Technologies for Point of Care Testing: Progress and Perspectives.

Abstract: Since the Human Genome Project completed in 2000, the sequencing of the first genome, massive progress has been made by medical science in the early diagnosis and personalized therapies based on nucleic acids (NA) analysis. To allow the extensive use of these molecular methods in medical practice, scientific research is nowadays strongly focusing on the development of new miniaturized and easy-to-use technologies and devices allowing fast and low cost NA analysis in decentralized environments. It is now the era of so-called genetic “Point-of-Care” (PoC). These systems must integrate and automate all steps necessary for molecular analysis such as sample preparation (extraction and purification of NA) and detection based on PCR (Polymerase Chain Reaction) technology in order to perform, by unskilled personnel, in vitro genetic analysis near the patient (in hospital, in the physician office, clinic, or home), with rapid answers and low cost. In this review, the recent advances in genetic PoC technologies are...

Performance Evaluation of Bluetooth Low Energy: A Systematic Review

Abstract: Small, compact and embedded sensors are a pervasive technology in everyday life for a wide number of applications (e.g., wearable devices, domotics, e-health systems, etc.). In this context, wireless transmission plays a key role, and among available solutions, Bluetooth Low Energy (BLE) is gaining more and more popularity. BLE merges together good performance, low-energy consumption and widespread diffusion. The aim of this work is to review the main methodologies adopted to investigate BLE performance. The first part of this review is an in-depth description of the protocol, highlighting the main characteristics and implementation details. The second part reviews the state of the art on BLE characteristics and performance. In particular, we analyze throughput, maximum number of connectable sensors, power consumption, latency and maximum reachable range, with the aim to identify what are the current limits of BLE technology. The main results can be resumed as follows: throughput may theoretically reach the limit of ~230 kbps, but actual applications analyzed in this review show throughputs limited to ~100 kbps; the maximum reachable range is strictly dependent on the radio power, and it goes up to a few tens of meters; the maximum number of nodes in the network depends on connection parameters, on the network architecture and specific device characteristics, but it is usually lower than 10; power consumption and latency are largely modeled and analyzed and are strictly dependent on a huge number of parameters. Most of these characteristics are based on analytical models, but there is a need for rigorous experimental evaluations to understand the actual limits.

Nanowire FET Based Neural Element for Robotic Tactile Sensing Skin.

Abstract: This paper presents novel Neural Nanowire Field Effect Transistors (υ-NWFETs) based hardware-implementable neural network (HNN) approach for tactile data processing in electronic skin (e-skin). The viability of Si nanowires (NWs) as the active material for υ-NWFETs in HNN is explored through modeling and demonstrated by fabricating the first device. Using υ-NWFETs to realize HNNs is an interesting approach as by printing NWs on large area flexible substrates it will be possible to develop a bendable tactile skin with distributed neural elements (for local data processing, as in biological skin) in the backplane. The modeling and simulation of υ-NWFET based devices show that the overlapping areas between individual gates and the floating gate determines the initial synaptic weights of the neural network - thus validating the working of υ-NWFETs as the building block for HNN. The simulation has been further extended to υ-NWFET based circuits and neuronal computation system and this has been validated by interfacing it with a transparent tactile skin prototype (comprising of 6 × 6 ITO based capacitive tactile sensors array) integrated on the palm of a 3D printed robotic hand. In this regard, a tactile data coding system is presented to detect touch gesture and the direction of touch. Following these simulation studies, a four-gated υ-NWFET is fabricated with Pt/Ti metal stack for gates, source and drain, Ni floating gate, and Al2O3 high-k dielectric layer. The current-voltage characteristics of fabricated υ-NWFET devices confirm the dependence of turn-off voltages on the (synaptic) weight of each gate. The presented υ-NWFET approach is promising for a neuro-robotic tactile sensory system with distributed computing as well as numerous futuristic applications such as prosthetics, and electroceuticals.

A 94-GHz 4TX–4RX Phased-Array FMCW Radar Transceiver With Antenna-in-Package

Abstract: A 94-GHz phased-array transceiver IC for frequency modulated continuous wave (FMCW) radar with four transmitters, four receivers, and integrated LO generation has been designed and fabricated in a 130-nm SiGe BiCMOS technology, and integrated into an antenna-in-package module. The transceiver, targeting gesture recognition applications for mobile devices, has been designed using phased-array techniques to reduce the total DC power while still maintaining the required link budget for FMCW operation. The complete array achieves state-of-the-art for W-band per-element power consumption of 106 mW per TX element and 91 mW per RX element, and measurements indicate a per-element output power of 6.4 dBm and single-sideband noise figure of 12.5 dB at 94 GHz. The array is able to achieve a beam steering range of ±20° while maintaining at least 3 dB main lobe to side lobe levels. The complete chip-antenna module has been tested to characterize basic FMCW radar functionality. Initial radar experiments suggest a sub-5-cm range resolution is possible with 3.68 GHz RF sweep bandwidth, which is in line with theoretical predictions.

Performance and design considerations for gate-all-around stacked-NanoWires FETs

Abstract: This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs Key technological challenges will be discussed and recent research results presented Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

Abstract: This paper presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 $\mu \text{m}$ by 250 $\mu \text{m}$ . The proof-of-concept receiver was implemented in an STMicroelectronics’s 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a $4 \times 4$ subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables an efficient in-pixel A/D conversion. The per-pixel switched-capacitor $\Delta \Sigma $ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator’s measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1-V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. The functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.

Integrated waveguide PIN photodiodes exploiting lateral Si/Ge/Si heterojunction.

Abstract: Germanium photodetectors are considered to be mature components in the silicon photonics device library. They are critical for applications in sensing, communications, or optical interconnects. In this work, we report on design, fabrication, and experimental demonstration of an integrated waveguide PIN photodiode architecture that calls upon lateral double Silicon/Germanium/Silicon (Si/Ge/Si) heterojunctions. This photodiode configuration takes advantage of the compatibility with contact process steps of silicon modulators, yielding reduced fabrication complexity for transmitters and offering high-performance optical characteristics, viable for high-speed and efficient operation near 1.55 μm wavelengths. More specifically, we experimentally obtained at a reverse voltage of 1V a dark current lower than 10 nA, a responsivity higher than 1.1 A/W, and a 3 dB opto-electrical cut-off frequency over 50 GHz. The combined benefits of decreased process complexity and high-performance device operation pave the way towards attractive integration strategies to deploy cost-effective photonic transceivers on silicon-on-insulator substrates.

Si/SiGe:C and InP/GaAsSb Heterojunction Bipolar Transistors for THz Applications

Abstract: This paper presents Si/SiGe:C and InP/GaAsSb HBTs which feature specific assets to address submillimeter-wave and THz applications. Process and modeling status and challenges are reviewed. The specific topics of thermal and substrate effects, reliability, and HF measurements are also discussed.

L-shaped fiber-chip grating couplers with high directionality and low reflectivity fabricated with deep-UV lithography

Abstract: Grating couplers enable position-friendly interfacing of silicon chips by optical fibers. The conventional coupler designs call upon comparatively complex architectures to afford efficient light coupling to sub-micron silicon-on-insulator (SOI) waveguides. Conversely, the blazing effect in double-etched gratings provides high coupling efficiency with reduced fabrication intricacy. In this Letter, we demonstrate for the first time, to the best of our knowledge, the realization of an ultra-directional L-shaped grating coupler, seamlessly fabricated by using 193 nm deep-ultraviolet (deep-UV) lithography. We also include a subwavelength index engineered waveguide-to-grating transition that provides an eight-fold reduction of the grating reflectivity, down to 1% (−20 dB). A measured coupling efficiency of −2.7 dB (54%) is achieved, with a bandwidth of 62 nm. These results open promising prospects for the implementation of efficient, robust, and cost-effective coupling interfaces for sub-micrometric SOI waveguides, as desired for large-volume applications in silicon photonics.

Review Article: Recommended reading list of early publications on atomic layer deposition—Outcome of the “Virtual Project on the History of ALD”

Abstract: Atomic layer deposition (ALD), a gas-phase thin film deposition technique based on repeated, self-terminating gas-solid reactions, has become the method of choice in semiconductor manufacturing and many other technological areas for depositing thin conformal inorganic material layers for various applications. ALD has been discovered and developed independently, at least twice, under different names: atomic layer epitaxy (ALE) and molecular layering. ALE, dating back to 1974 in Finland, has been commonly known as the origin of ALD, while work done since the 1960s in the Soviet Union under the name "molecular layering" (and sometimes other names) has remained much less known. The virtual project on the history of ALD (VPHA) is a volunteer-based effort with open participation, set up to make the early days of ALD more transparent. In VPHA, started in July 2013, the target is to list, read and comment on all early ALD academic and patent literature up to 1986. VPHA has resulted in two essays and several presentations at international conferences. This paper, based on a poster presentation at the 16th International Conference on Atomic Layer Deposition in Dublin, Ireland, 2016, presents a recommended reading list of early ALD publications, created collectively by the VPHA participants through voting. The list contains 22 publications from Finland, Japan, Soviet Union, United Kingdom, and United States. Up to now, a balanced overview regarding the early history of ALD has been missing; the current list is an attempt to remedy this deficiency.

A 0.92-THz SiGe Power Radiator Based on a Nonlinear Theory for Harmonic Generation

Abstract: We propose a nonlinear device model and a systematic methodology to generate maximum power at any desired harmonic. The proposed power optimization technique is based on the Volterra-Wiener theory of nonlinear systems. By manipulating the device nonlinearity and optimizing the embedding network, optimum conditions for harmonic power generation are provided. Using this theory, a 920–944-GHz frequency quadrupler is designed in a 130-nm SiGe:C process. The circuit achieves the peak output power of −17.3 and −10 dBm of effective isotropic radiated power and consumes 5.7 mW of dc power. To the best of our knowledge, this circuit demonstrates the highest generated power among Si/SiGe-based sources at this frequency range.

Inhibition of Aβ Amyloid Growth and Toxicity by Silybins: The Crucial Role of Stereochemistry

Abstract: The self-assembling of the amyloid β (Aβ) peptide into neurotoxic aggregates is considered a central event in the pathogenesis of Alzheimer’s disease (AD) Based on the “amyloid hypothesis”, many efforts have been devoted to designing molecules able to halt disease progression by inhibiting Aβ self-assembly Here, we combine biophysical (ThT assays, TEM and AFM imaging), biochemical (WB and ESI-MS), and computational (all-atom molecular dynamics) techniques to investigate the capacity of four optically pure components of the natural product silymarin (silybin A, silybin B, 2,3-dehydrosilybin A, 2,3-dehydrosilybin B) to inhibit Aβ aggregation Despite TEM analysis demonstrated that all the four investigated flavonoids prevent the formation of mature fibrils, ThT assays, WB and AFM investigations showed that only silybin B was able to halt the growth of small-sized protofibrils thus promoting the formation of large, amorphous aggregates Molecular dynamics (MD) simulations indicated that silybin B interacts

A 170-GHz Fully Integrated Single-Chip FMCW Imaging Radar with 3-D Imaging Capability

Abstract: A 170-GHz fully integrated single-chip heterodyne frequency modulated continuous-wave (FMCW) imaging radar using a 130-nm SiGe BiCMOS technology ( $f_{T}/f_{\max } = 220/280$ GHz) is reported. This system demonstrates a wide bandwidth of 27.5 GHz (16.3%) at a center frequency of 168 GHz. A design methodology to maximize the tuning range of the voltage-controlled oscillator (VCO) is presented. A co-design of the VCO, coupler, and antenna is performed to minimize the chip area and the dc power consumption. The transmitter radiates a peak power of −1 dBm with a dc-to-RF efficiency of 1.42%. At the receiver side, a subharmonic mixer is used for signal down-conversion. The system achieves a measured sensitivity of 87 fW with a total dc power consumption of 67 mW. The prototype is capable of forming 2-D and 3-D images with a range resolution of 7 mm. To the best of our knowledge, this fully integrated imaging radar demonstrates the highest sensitivity and radiation efficiency among all imaging systems around 200 GHz. Moreover, the system is capable of practical 2-D and 3-D imaging with significantly lower dc power consumption compared to the state-of-the-art FMCW radars.

Vertical gate-all-around TFET

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

3D Sequential Integration: Application-driven technological achievements and guidelines

Abstract: 3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (<100nm) offers new 3D partitioning options at fine granularities. This paper reviews potential applications ranging from computing to sensor interface and gives an update on 3DSI device development. Low-temperature processing techniques have made great progress and High Performance (HP) digital stacked FETs for computing application can be achieved with a 500°C Thermal Budget (TB). In addition, ULK/metal lines capable of withstanding this TB can be used between stacked tiers. Ultra-Low TB FETs (<400°C) have potential for low-power applications and allow for the stacking of multiple layers.

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Abstract: We present a complete pixel based on a single-photon avalanche diode (SPAD) fabricated in a backside-illuminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65-nm image sensor technology and a data processing tier in 40-nm CMOS. Using a simple, CMOS-compatible technique, the pixel is capable of passive quenching and active recharge at voltages well above those imposed by a single transistor whilst ensuring that the reliability limits across the gate-source ( $\text {V} _{\text {GS}}$ ), gate-drain ( $\text {V} _{\text {GD}}$ ) and drain–source ( $\text {V} _{\text {DS}}$ ) are not exceeded for any device. For a given technology, the circuit extends the maximum excess bias that SPADs can be operated at when using transistors as quenching elements, thus improving the SPAD sensitivity, timing performance, and photon detection probability uniformity. Implemented with 2.5-V thick oxide transistors and operated at 4.4-V excess bias, the design achieves a timing jitter of 95-ps full-width at half maximum, maximum photon detection efficiency (PDE) of 21.9% at 660 nm and 0.08% afterpulsing probability with a dead time of 8 ns. This is both the lowest afterpulsing probability at 8-ns dead time and the highest peak PDE for a BSI SPAD in a 3D IC technology to date.

Heavy Ion Induced Degradation in SiC Schottky Diodes: Bias and Energy Deposition Dependence

Abstract: Experimental results on ion-induced leakage current increase in 4H-SiC Schottky power diodes are presented. Monte Carlo and TCAD simulations show that degradation is due to the synergy between applied bias and ion energy deposition. This degradation is possibly related to thermal spot annealing at the metal semiconductor interface. This thermal annealing leads to an inhomogeneity of the Schottky barrier that could be responsible for the increase leakage current as a function of fluence.

Fully Depleted Silicon on Insulator Devices CMOS: The 28-nm Node Is the Perfect Technology for Analog, RF, mmW, and Mixed-Signal System-on-Chip Integration

Abstract: The race on the Complementary Metal-Oxide-Semiconductor (CMOS) More Moore integration scale has brought to light several major limitations for efficient planar process integration starting with the 40 nm technology node. The transistor channel was more and more difficult to control in terms of electrostatics, and many process engineering methods (such as, for example, Silicon strain) were used to provide transistors with good carrier speed and decent electrical characteristics. Starting from the 28-nm node, the obvious solution for transistors with increased electrical performances was the use of fully depleted devices. Two integration methods have been identified by the semiconductor industry for these fully depleted devices: Fully Depleted Silicon on Insulator (FD-SOI) CMOS and Fin-FET CMOS devices. While the fundamental carrier semiconductor equations are similar, the process integration is very different. This article focuses on planar FDSOI CMOS technology features as integrated by STMicroelectronics in the 28-nm node [1], [2], and its specificities for analog, radio frequency (RF), millimeter wave (mmW), and mixed signal systemon-chip (SoC) integration.

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Abstract: This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achieves 193 million operations per second (MOPS) per mW at 162 MOPS (32 bits), improving the first-generation Parallel Ultra-Low-Power (PULP) architecture by 6.4 and 3.2 times in performance and energy efficiency, respectively.

Farfalle: parallel permutation-based cryptography

Abstract: In this paper, we introduce Farfalle , a new permutation-based construction for building a pseudorandom function (PRF). The PRF takes as input a key and a sequence of arbitrary-length data strings, and returns an arbitrary-length output. It has a compression layer and an expansion layer , each involving the parallel application of a permutation. The construction also makes use of LFSR-like rolling functions for generating input and output masks and for updating the inner state during expansion. On top of the inherent parallelism, Farfalle instances can be very efficient because the construction imposes less requirements on the underlying primitive than, e.g., the duplex construction or typical block cipher modes. Farfalle has an incremental property: compression of common prefixes of inputs can be factored out. Thanks to its input-output characteristics, Farfalle is really versatile. We specify simple modes on top of it for authentication, encryption and authenticated encryption, as well as a wide block cipher mode. As a showcase, we present Kravatte, a very efficient instance of Farfalle based on Keccak- p [1600, n r ] permutations and formulate concrete security claims against classical and quantum adversaries. The permutations in the compression and expansion layers of Kravatte have only 6 rounds apiece and the rolling functions are lightweight. We provide a rationale for our choices and report on software performance.

Translation-Invariant Multiscale Energy-Based PCA for Monitoring Batch Processes in Semiconductor Manufacturing

Abstract: The overwhelming majority of processes taking place in semiconductor manufacturing operate in a batch mode by imposing time-varying conditions to the products in a cyclic and repetitive fashion. These conditions make process monitoring a very challenging task, especially in massive production plants. Among the state-of-the-art approaches proposed to deal with this problem, the so-called multiway methods incorporate the batch dynamic features in a normal operation model at the expense of estimating a large number of parameters. This makes these approaches prone to overfitting and instability. Moreover, batch trajectories are required to be well aligned in order to provide the expected performance. To overcome these issues and other limitations of the conventional methodologies for process monitoring in semiconductor manufacturing, we propose an approach, translation-invariant multiscale energy-based principal component analysis, that requires a much lower number of estimated parameters. It is free of process trajectory alignment requirements and thus easier to implement and maintain, while still rendering useful information for fault detection and root cause analysis. The proposed approach is based on implementing a translation-invariant wavelet decomposition along the time series profile of each variable in one batch. The normal operational signatures in the time-frequency domain are extracted, modeled, and then used for process monitoring, allowing prompt detection of process abnormalities. The proposed procedure was tested with real industrial data and it proved to effectively detect the existing faults as well as to provide reliable indications of their underlying root causes.

Modéliser l’émergence de l’expertise et sa gouvernance dans les entreprises innovantes : des communautés aux sociétés proto-épistémiques d’experts

Abstract: Dans les industries de hautes technologies, le rythme contemporain de l’innovation se caracterise aujourd’hui par un renouvellement accelere des produits et par une destabilisation des dominant designs. Dans ce contexte d’innovation intensive, les organisations industrielles se doivent de se doter de nouvelles capacites d’innovation de rupture pour organiser l’emergence de nouvelles expertises technologiques afin de permettre la conception innovante de nouveaux produits et technologies. Paradoxalement, les enjeux d’expertise et de conception innovante peuvent parfois sembler en opposition ou du moins en tension. L’expertise semble preserver les dominant designs, mais c’est aussi elle qui permet la generation d’expansion conceptuelle. Derriere cette aporie, se posent des questions cruciales sur le management contemporain de l’emergence de l’expertise dans les organisations industrielles en situation d’innovation intensive. A partir d’une demarche exploratoire basee sur une etude de cas longitudinale chez STMicroelectronics, cette these s’interesse aux modeles de gouvernance de l’emergence de l’expertise dans les organisations industrielles. A partir d’une analyse empirique chez STMicroelectronics, ces travaux mettent en evidence que l’emergence de nouvelles expertises s’effectue par une reorganisation et une restructuration profonde des structures d’expertise. Autrement dit, les nouveaux domaines d’expertise emergent a partir de la recomposition des relations d’interdependance entre les domaines d’expertises existants. Par ailleurs, ces travaux de recherche proposent un modele formel de l’emergence de l’expertise dans les organisations industrielles. Ce modele permet d’identifier de nouveaux enjeux manageriaux et de mettre en evidence des modeles organisationnels permettant de supporter ces formes d’emergence d’expertise. De nouvelles solutions manageriales sont ensuite experimentees et analysees chez STMicroelectronics. Enfin, la these propose une analyse des roles et missions des experts scientifiques dans les strategies d’exploration et d’innovation au sein des organisations industrielles.

SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping

Abstract: Achieving wireless communications at 5–30 Mb/s in energy-harvesting Internet-of-Things (IoT) applications requires energy efficiencies better than 100 pJ/b. Impulse-radio ultrawideband (UWB) communications offer an efficient way to achieve high data rate at ultralow power for short-range links. We propose a digital UWB transmitter (TX) system-on-chip (SoC) designed for ultralow voltage in 28-nm FDSOI CMOS. It features a PLL-free architecture, which exploits the duty-cycling nature of impulse radio through aggressive duty cycling within the pulse modulation time slot for high energy efficiency and minimum jitter accumulation. Wide-range on-chip adaptive forward back biasing is used for threshold voltage reduction, PVT compensation, and tuning of both the carrier frequency and the output power. To ensure spectral compliance with output power regulations without the use of bulky and expensive off-chip filters, a programmable pulse-shaping functionality is integrated in the digital power amplifier based on a 7–9-GS/s, 5-b current DAC. Operated at 0.55 V, it achieves a record energy efficiency of 14 pJ/b for the TX alone and 24 pJ/b for the complete SoC with embedded power management. The TX SoC occupies a core area of 0.93 mm2.