Showing papers by "STMicroelectronics published in 2019"

An Overview of Normally-Off GaN-Based High Electron Mobility Transistors.

Abstract: Today, the introduction of wide band gap (WBG) semiconductors in power electronics has become mandatory to improve the energy efficiency of devices and modules and to reduce the overall electric power consumption in the world. Due to its excellent properties, gallium nitride (GaN) and related alloys (e.g., AlxGa1−xN) are promising semiconductors for the next generation of high-power and high-frequency devices. However, there are still several technological concerns hindering the complete exploitation of these materials. As an example, high electron mobility transistors (HEMTs) based on AlGaN/GaN heterostructures are inherently normally-on devices. However, normally-off operation is often desired in many power electronics applications. This review paper will give a brief overview on some scientific and technological aspects related to the current normally-off GaN HEMTs technology. A special focus will be put on the p-GaN gate and on the recessed gate hybrid metal insulator semiconductor high electron mobility transistor (MISHEMT), discussing the role of the metal on the p-GaN gate and of the insulator in the recessed MISHEMT region. Finally, the advantages and disadvantages in the processing and performances of the most common technological solutions for normally-off GaN transistors will be summarized.

A Reconfigurable 3-D-Stacked SPAD Imager With In-Pixel Histogramming for Flash LIDAR or High-Speed Time-of-Flight Imaging

Abstract: A 256 $\times $ 256 single-photon avalanche diode (SPAD) sensor integrated into a 3-D-stacked 90-nm 1P4M/40-nm 1P8M process is reported for flash light detection and ranging (LIDAR) or high-speed direct time-of-flight (ToF) 3-D imaging. The sensor bottom tier is composed of a 64 $\times $ 64 matrix of 36.72- $\mu \text{m}$ pitch modular photon processing units which operate from shared $4\,\,\times $ 4 SPADs at 9.18- $\mu \text{m}$ pitch and 51% fill-factor. A 16 $\times $ 14 bit counter array integrates photon counts or events to compress data to 31.4 Mb/s at 30-frame/s readout over 8 I/O operating at 100 MHz. The pixel-parallel multi-event time-to-digital converter (TDC) approach employs a programmable internal or external clock for 0.56–560-ns time bin resolution. In conjunction with a per-pixel correlator, the power is reduced to less than 100 mW in practical daylight ranging scenarios. Examples of ranging and high-speed 3-D ToF applications are given.

A Saliency-Based Convolutional Neural Network for Table and Chart Detection in Digitized Documents

Abstract: Within the realm of information extraction from documents, detection of tables and charts is particularly needed as they contain a visual summary of the most valuable information contained in a document. For a complete automation of the visual information extraction process from tables and charts, it is necessary to develop techniques that localize them and identify precisely their boundaries. In this paper we aim at solving the table/chart detection task through an approach that combines deep convolutional neural networks, graphical models and saliency concepts. In particular, we propose a saliency-based fully-convolutional neural network performing multi-scale reasoning on visual cues followed by a fully-connected conditional random field (CRF) for localizing tables and charts in digital/digitized documents. Performance analysis, carried out on an extended version of the ICDAR 2013 (with annotated charts as well as tables) dataset, shows that our approach yields promising results, outperforming existing models.

Autonomous Energy-Efficient Wireless Sensor Network Platform for Home/Office Automation

Abstract: Smart homes/offices based on wireless sensor networks (WSNs) can provide an assisted living and working environment to the users. In these applications, the distributed network nodes are made up of low-power low-cost high-energy-efficient electronic platforms equipped with sensors, microcontroller, radio, and antenna, able to periodically sense, receive, store, pre-process, and transmit ambient data to a remote host station. Conventional nodes are usually supplied by batteries, resulting in a significant limitation to the lifetime and to the maximum number of deployable devices. To meet the demand of the next Internet-of-Things (IoT) applications, requiring a vast plurality of interconnected wireless network nodes, this paper presents the design and implementation of a WSN platform whose nodes are energetically autonomous thanks to an embedded photovoltaic panel associated to a rechargeable battery and a power-efficient design with optimized power-management strategy. The implemented node is able to harvest indoor ambient light starting from 100 lux and, according to the available energy, adaptively sets the sensors acquisition and RF transmission rate. Moreover, it provides long-distance data transmission with air data rate from 1 to 500 kbps. The WSN node device is implemented on an $8.6\times 5.4$ cm2 flexible PCB, being therefore amenable to conform even to curved surfaces. Comparison with the commercial IoT nodes reveals a significant improvement in the state of the art.

Overview of the JET preparation for deuterium–tritium operation with the ITER like-wall

Abstract: For the past several years, the JET scientific programme (Pamela et al 2007 Fusion Eng. Des. 82 590) has been engaged in a multi-campaign effort, including experiments in D, H and T, leading up to 2020 and the first experiments with 50%/50% D–T mixtures since 1997 and the first ever D–T plasmas with the ITER mix of plasma-facing component materials. For this purpose, a concerted physics and technology programme was launched with a view to prepare the D–T campaign (DTE2). This paper addresses the key elements developed by the JET programme directly contributing to the D–T preparation. This intense preparation includes the review of the physics basis for the D–T operational scenarios, including the fusion power predictions through first principle and integrated modelling, and the impact of isotopes in the operation and physics of D–T plasmas (thermal and particle transport, high confinement mode (H-mode) access, Be and W erosion, fuel recovery, etc). This effort also requires improving several aspects of plasma operation for DTE2, such as real time control schemes, heat load control, disruption avoidance and a mitigation system (including the installation of a new shattered pellet injector), novel ion cyclotron resonance heating schemes (such as the threeions scheme), new diagnostics (neutron camera and spectrometer, active Alfven eigenmode antennas, neutral gauges, radiation hard imaging systems…) and the calibration of the JET neutron diagnostics at 14 MeV for accurate fusion power measurement. The active preparation of JET for the 2020 D–T campaign provides an incomparable source of information and a basis for the future D–T operation of ITER, and it is also foreseen that a large number of key physics issues will be addressed in support of burning plasmas.

Strategies and Techniques for Powering Wireless Sensor Nodes through Energy Harvesting and Wireless Power Transfer.

Abstract: The continuous development of internet of things (IoT) infrastructure and applications is paving the way for advanced and innovative ideas and solutions, some of which are pushing the limits of state-of-the-art technology. The increasing demand for Wireless Sensor Nodes (WSNs) able to collect and transmit data through wireless communication channels, while often positioned in locations that are difficult to access, is driving research into innovative solutions involving energy harvesting (EH) and wireless power transfer (WPT) to eventually allow battery-free sensor nodes. Due to the pervasiveness of radio frequency (RF) energy, RF EH and WPT are key technologies with the potential to power IoT devices and smart sensing architectures involving nodes that need to be wireless, maintenance free, and sufficiently low in cost to promote their use almost anywhere. This paper presents a state-of-the-art, ultra-low power 2.5 μ W highly integrated mixed signal system on chip (SoC), for multi-source energy harvesting and wireless power transfer. It introduces a novel architecture that integrates an ultra-low power intelligent power management, an RF to DC converter with very low power sensitivity and high power conversion efficiency (PCE), an Amplitude-Shift-Keying/Frequency-Shift-Keying (ASK/FSK) receiver and digital circuitry to achieve the advantage to cope, in a versatile way and with minimal use of external components, with the wide variety of energy sources and use cases. Diverse methods for powering Wireless Sensor Nodes through energy harvesting and wireless power transfer are implemented providing related system architectures and experimental results.

5.7 A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager

Abstract: Light Detection and Ranging (LIDAR) applications pose extremely challenging dynamic range (DR) requirements on optical time-of-flight (ToF) receivers due to laser returns affected by the inverse square law over 2-3 decades of distance, diverse target reflectivity, and high solar background [1]. Integrated CMOS SPADs have a native DR exceeding 140dB, typically extending from the noise floor of few cps to 100’s Mcps peak rate. To deliver this DR to downstream DSP, large SPAD time-resolved imaging arrays must count and time billions of single photon events per second demanding massively parallel on-chip pixel processing to achieve practical I/O power consumption and data rates. Hybrid Cu-Cu bonding offers a mass-manufacturable platform to implement these sensors by providing high-fill-factor SPADs optimised for NIR stacked on dense nanoscale digital processors [2]. Stacked sensor architectures involving pixel-level histogramming, on-chip peak detection and TDC/processor resource sharing are now being investigated [3–5].

25 Gbps low-voltage hetero-structured silicon-germanium waveguide pin photodetectors for monolithic on-chip nanophotonic architectures

Abstract: Near-infrared germanium (Ge) photodetectors monolithically integrated on top of silicon-on-insulator substrates are universally regarded as key enablers towards chip-scale nanophotonics, with applications ranging from sensing and health monitoring to object recognition and optical communications. In this work, we report on the high-data-rate performance pin waveguide photodetectors made of a lateral hetero-structured silicon-Ge-silicon (Si-Ge-Si) junction operating under low reverse bias at 1.55 μm. The pin photodetector integration scheme considerably eases device manufacturing and is fully compatible with complementary metal-oxide-semiconductor technology. In particular, the hetero-structured Si-Ge-Si photodetectors show efficiency-bandwidth products of ∼9 GHz at −1 V and ∼30 GHz at −3 V, with a leakage dark current as low as ∼150 nA, allowing superior signal detection of high-speed data traffic. A bit-error rate of 10−9 is achieved for conventional 10 Gbps, 20 Gbps, and 25 Gbps data rates, yielding optical power sensitivities of −13.85 dBm, −12.70 dBm, and −11.25 dBm, respectively. This demonstration opens up new horizons towards cost-effective Ge pin waveguide photodetectors that combine fast device operation at low voltages with standard semiconductor fabrication processes, as desired for reliable on-chip architectures in next-generation nanophotonics integrated circuits.

Wearable Sensors System for an Improved Analysis of Freezing of Gait in Parkinson's Disease Using Electromyography and Inertial Signals.

Abstract: We propose a wearable sensor system for automatic, continuous and ubiquitous analysis of Freezing of Gait (FOG), in patients affected by Parkinson’s disease. FOG is an unpredictable gait disorder with different clinical manifestations, as the trembling and the shuffling-like phenotypes, whose underlying pathophysiology is not fully understood yet. Typical trembling-like subtype features are lack of postural adaptation and abrupt trunk inclination, which in general can increase the fall probability. The targets of this work are detecting the FOG episodes, distinguishing the phenotype and analyzing the muscle activity during and outside FOG, toward a deeper insight in the disorder pathophysiology and the assessment of the fall risk associated to the FOG subtype. To this aim, gyroscopes and surface electromyography integrated in wearable devices sense simultaneously movements and action potentials of antagonist leg muscles. Dedicated algorithms allow the timely detection of the FOG episode and, for the first time, the automatic distinction of the FOG phenotypes, which can enable associating a fall risk to the subtype. Thanks to the possibility of detecting muscles contractions and stretching exactly during FOG, a deeper insight into the pathophysiological underpinnings of the different phenotypes can be achieved, which is an innovative approach with respect to the state of art.

Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs described with Band Broadening

Abstract: In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by $SS(T) = \ln10~k_BT/e$. However, recent low-temperature studies of different advanced CMOS technologies have reported $SS$(4K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of $SS(T)$ in 28nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying Fermi-Dirac statistics. This results in a subthreshold $I_{D}\sim e^{eV_{GS}/k_BT_0}$ for $T_0=35$K with saturation value $SS(T

Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures

Abstract: We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects process and characterization. 3D packaging is presented up to the successful structural test and characterization of the demonstrator.

A Review on Power Supply Induced Jitter

Abstract: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS

Abstract: A four-level pulse-amplitude modulation (PAM-4) transceiver operating up to 64 Gb/s in 28-nm CMOS fully depleted silicon-on-insulator (FDSOI) for short-reach electrical links is presented. The receiver equalization relies on a flexible continuous-time linear equalizer (CTLE), providing a very accurate channel inversion through a transfer function that can be optimally adapted at low frequency, mid-frequency, and high frequency independently. The CTLE meets the performance requirements of CEI-56G-VSR without requiring the decision feedback equalizer (DFE) implementation. As a result, timing constraints for comparators in data and edge sampling paths may be relaxed by using track-and-hold (T&H) stages, saving power consumption. At the maximum speed, the receiver draws 180 mA from 1-V supply, corresponding to 2.8 mW/Gb/s only. The transmitter embeds a flexible feed-forward equalizer (FFE) which can be reconfigured to comply with legacy standards. A comparison between current-mode (CM) and voltage-mode (VM) TX drivers is proposed, proving through experiments that the latter yields larger PAM-4 eye openings, thanks to the intrinsically higher speed. The full transceiver (TX, RX, and clock generation) operates from 16 to 64 Gb/s in PAM-4 and 8 to 32 Gb/s in non-return-to-zero (NRZ), and supports 2 $\times $ and 4 $\times $ oversampling to reduce data rate down to 2 Gb/s. A TX-to-RX link at 64 Gb/s, across a 16.8-dB-loss channel, reaches 10−12 minimum bit-error rate (BER) and 0.19-UI horizontal eye opening at BER = 10−6, with 5.02 mW/Gb/s power dissipation.

A 115–135-GHz 8PSK Receiver Using Multi-Phase RF-Correlation-Based Direct-Demodulation Method

Abstract: This paper presents the theory, design, and implementation of an 8PSK direct-demodulation receiver based on a novel multi-phase RF-correlation concept. The output of this RF-to-bits receiver architecture is demodulated bits, obviating the need for power-hungry high-speed-resolution data converters. A single-channel 115–135-GHz receiver prototype was fabricated in a 55-nm SiGe BiCMOS process. A max conversion gain of 32 dB and a min noise figure (NF) of 10.3 dB were measured. A data rate of 36 Gb/s was wirelessly measured at 30-cm distance with the received 8PSK signal being directly demodulated on-chip at a bit-error rate (BER) of 1e-6. The measured receiver sensitivity at this BER is −41.28 dBm. The prototype occupies 2.5 $\times $ 3.5 mm2 of die area, including PADs and test circuits (2.5-mm2 active area), and consumes a total dc power of 200.25 mW.

Self-Heating Effect in FDSOI Transistors Down to Cryogenic Operation at 4.2 K

Abstract: Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ( $\Delta {T}$ ) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature ( ${T}_{\text {Device}}$ ) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work.

Chemical phase segregation during the crystallization of Ge-rich GeSbTe alloys

Abstract: Ge-rich Ge–Sb–Te alloys are materials with potential for new non-volatile memories named Phase Change Memories offering an extended range of possible applications. However, the origin of their superior properties, notably their much higher transition temperature and increased thermal stability, is unknown. Using a variety of transmission electron microscopy based techniques, we have investigated the changes that affect the structure and composition of such alloys during thermal annealing. We show that, although Ge-rich Ge–Sb–Te materials can be grown as amorphous layers of homogeneous compositions, the primary effect of annealing is to activate phase separation between stable Ge and Ge–Sb–Te phases. This phase separation starts at 380 °C while the material is still amorphous and leads to the nucleation of the first Ge nanocrystals. Increasing the annealing temperature to 400 and then to 450 °C allows the crystalline Ge phase to grow by driving the Ge excess out of the matrix, which, finally, leads to the formation of large (30–50 nm) crystals with the face-centered-cubic Ge–Sb–Te structure. After annealing at 500 °C for 30 minutes, the layer fully crystallizes and consists of a population of large (50–100 nm) face-centered-cubic Ge–Sb–Te crystals with a stoichiometry close to 225 buried in a matrix composed of small Ge nanocrystals. This study evidences that the superior properties of Ge-rich alloys do not result from the intrinsic properties of some Ge-rich crystalline phases but from kinetic factors. The formation of a two phase Ge/Ge–Sb–Te material involves long range diffusion of atomic species, first and foremost, Ge.

The Promise of Digital Biopsy for the Prediction of Tumor Molecular Features and Clinical Outcomes Associated With Immunotherapy.

Abstract: Immunotherapy by immune checkpoint inhibitors has emerged as an effective treatment for a slight proportion of patients with aggressive tumors. Currently, some molecular determinants, such as the expression of the programmed cell death ligand-1 (PD-L1) or the tumor mutational burden (TMB) have been used in the clinical practice as predictive biomarkers, although they fail in consistency, applicability, or reliability to precisely identify the responding patients mainly because of their spatial intratumoral heterogeneity. Therefore, new biomarkers for early prediction of patient response to immunotherapy, that could integrate several approaches, are eagerly sought. Novel methods of quantitative image analysis (such as radiomics or pathomics) might offer a comprehensive approach providing spatial and temporal information from macroscopic imaging features potentially predictive of underlying molecular drivers, tumor-immune microenvironment, tumor-related prognosis, and clinical outcome (in terms of response or toxicity) following immunotherapy. Preliminary results from radiomics and pathomics analysis have demonstrated their ability to correlate image features with PD-L1 tumor expression, high CD3 cell infiltration or CD8 cell expression, or to produce an image signature concordant with gene expression. Furthermore, the predictive power of radiomics and pathomics can be improved by combining information from other modalities, such as blood values or molecular features, leading to increase the accuracy of these models. Thus, "digital biopsy," which could be defined by non-invasive and non-consuming digital techniques provided by radiomics and pathomics, may have the potential to allow for personalized approach for cancer patients treated with immunotherapy.

Sub-decibel silicon grating couplers based on L-shaped waveguides and engineered subwavelength metamaterials.

Abstract: The availability of low-loss optical interfaces to couple light between standard optical fibers and high-index-contrast silicon waveguides is essential for the development of chip-integrated nanophotonics. Input and output couplers based on diffraction gratings are attractive coupling solutions. Advanced grating coupler designs, with Bragg or metal mirror underneath, low- and high-index overlays, and multi-level or multi-layer layouts, have proven less useful due to customized or complex fabrication, however. In this work, we propose a rather simpler in design of efficient off-chip fiber couplers that provide a simulated efficiency up to 95% (−0.25 dB) at a wavelength of 1.55 µm. These grating couplers are formed with an L-shaped waveguide profile and synthesized subwavelength grating metamaterials. This concept jointly provides sufficient degrees of freedom to simultaneously control the grating directionality and out-radiated field profile of the grating mode. The proposed chip-to-fiber couplers promote robust sub-decibel coupling of light, yet contain device dimensions (> 120 nm) compatible with standard lithographic technologies presently available in silicon nanophotonic foundries. Fabrication imperfections are also investigated. Dimensional offsets of ± 15 nm in shallow-etch depth and ± 10 nm in linewidth’s and mask misalignments are tolerated for a 1-dB loss penalty. The proposed concept is meant to be universal, which is an essential prerequisite for developing reliable and low-cost optical couplers. We foresee that the work on L-shaped grating couplers with sub-decibel coupling efficiencies could also be a valuable direction for silicon chip interfacing in integrated nanophotonics.

29.7 A 500Mb/s -46.1dBm CMOS SPAD Receiver for Laser Diode Visible-Light Communications

Abstract: III-nitride laser diodes (LDs) are promising sources for light fidelity (LiFi) networks, underwater wireless optical communications (UWOC), and plastic optical fiber (POF) communications [1] due to their high modulation bandwidths ($\gt 5$GHz) compared to LEDs ($\lt 20$ MHz). Their narrow linewidths also enable robust free-space Gb/s LiFi links in the presence of high intensities of sunlight through selective spectral filtering. Fully integrated CMOS visible light communications (VLC) receivers have recently been developed to enable miniaturised and low cost Gb/s LD-based links [2]. Sensitivity of these devices is constrained by electrical noise sources such as thermal, shot or excess noise related to the employment of PIN photodiodes (PDs) or linear avalanche photodiodes (APDs) and their amplification circuits. The extremely high gain of SPADs operating in Geiger mode allows quantum sensitivity limits to be approached [3], [4]. A SPAD receiver (RX) for fiber optic applications achieved 200Mb/s at $6.5\times 10 ^{-3}$ BER within 24dB of the quantum limit [3]. In this paper, we demonstrate a fully integrated CMOS SPAD RX SoC extending this data rate by $2.5 \times $to 500Mb/s, whilst improving sensitivity to -46.1dBm, reducing the margin to the quantum limit to only 15dB. Our RX architecture permits massively parallel (4096) photon event summation to be achieved at a high fill-factor (43%) and sample rate (800MHz). Detector redundancy obviates the requirement on current RX implementations that the SPAD dead time be matched to the symbol period to achieve the maximum data rate [3, 4, 5]. Another advantage is that complex modulation schemes such as OFDM or PAM can be applied for high spectral efficiency and multipath interference mitigation. We demonstrate the RX in a practical, background insensitive VLC link at 1m in 1klx ambient conditions using a 450nm LD. The higher power consumption and dead time pile-up nonlinearity of the SPADs at high signal levels, leads us to conclude that the practical use of this device to be in assistance (rather than replacement) of existing APD or PIN RXs for LiFi, UWOC and POF applications towards extended link range or maintaining a low rate link in highly scattering environments.

Chemical Ordering in Bimetallic FeCo Nanoparticles: From a Direct Chemical Synthesis to Application As Efficient High-Frequency Magnetic Material

Abstract: Single-crystalline FeCo nanoparticles with tunable size and shape were prepared by co-decomposing two metal-amide precursors under mild conditions. The nature of the ligands introduced in this organometallic synthesis drastically affects the reactivity of the precursors and, thus, the chemical distribution within the nanoparticles. The presence of the B2 short-range order was evidenced in FeCo nanoparticles prepared in the presence of HDAHCl ligands, combining 57Fe Mossbauer, zero-field 59Co ferromagnetic nuclear resonance (FNR), and X-ray diffraction studies. This is the first time that the B2 structure is directly formed during synthesis without the need of any annealing step. The as-prepared nanoparticles exhibit magnetic properties comparable with the ones for the bulk ( Ms = 226 Am2·kg-1). Composite magnetic materials prepared from these FeCo nanoparticles led to a successful proof-of-concept of the integration on inductor-based filters (27% enhancement of the inductance value at 100 MHz).

High-Performance Graphene/AlGaN/GaN Schottky Junctions for Hot Electron Transistors

Abstract: The electronic properties of the graphene (Gr) Schottky junction with an Al0.22Ga0.78N/GaN heterostructure on silicon have been investigated, both by experiment and with use of ab initio DFT calcul...

Advanced Motion-Tracking System with Multi-Layers Deep Learning Framework for Innovative Car-Driver Drowsiness Monitoring

Abstract: Recently, the ability to monitor driver drowsiness has attracted a great deal of attention in the automotive industry, in order to prevent the risk due to an inadequate driver psycho-physical state. Specifically, the research effort has focused on the study of the physiological signals to assess the attention level. The main idea consists in verifying the drowsiness level through analyzing the Heart Rate Variability (HRV). The HRV allows to understand the activity of the autonomic nervous system that regulates a series of unconscious and involuntary activities (e.g. the heartbeat, the blood pressure). The HRV is traditionally obtained from electrocardiography (ECG) even though the photoplethysmography (PPG) signal has been proposed as valid alternative to ECG in order to overcome some limitations derived from it. For the above reasons, we analyzed the skin micro-movements and changes in facial color due to blood circulation quite indistinguishable with naked eye in order to extract facial landmarks and to reconstruct PPG signal. The results we obtained by validation confirmed the correlation between the PPG signal detected by sensors and the reconstructed PPG signal from facial landmarks.

Electromagnetic Fault Injection : How Faults Occur

Abstract: Electromagnetic Fault Injection (EMFI) has recently gained popularity as a mean to induce faults because of its inherent advantages. Among them, the most interesting is probably its ability to generate faults in Systems on Chips without removing the package, and this even if only the frontside is exposed to the EM field. Despite this popularity, there is only little information on how EMFI generates faults. Within this context, this paper first aims at filling this lack by proposing a complete modeling of EM induction fault mechanism. In a second step, the introduced model is confronted to experimental data in order to demonstrate its soundness.

28 nm FDSOI analog and RF Figures of Merit at N2 cryogenic temperatures

Abstract: This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and maximum transconductance, gm_max, values are demonstrated. Current gain cutoff frequency, fT, increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space).

Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening

Abstract: In the standard MOSFET description of the drain current $ {I}_{{D}}$ as a function of applied gate voltage $ {V}_{{ {GS}}}$ , the subthreshold swing ${{SS(T)}}\equiv {{dV}}_{{{GS}}}/ {d}\log {I}_{ {D}}$ has a fundamental lower limit as a function of temperature ${T}$ given by ${ {SS(T)}}=\ln 10\,\, {k}_{ {B}} {T}/ {e}$ . However, recent low-temperature studies of different advanced CMOS technologies have reported SS (4 K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of SS(T) in 28 nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4 K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying the Fermi–Dirac statistics. This results in a subthreshold $ {I}_{ {D}}\sim {e}^{{{ {eV}}}_{{{GS}}}/ {k}_{ {B}} {T}_{0}}$ for $ {T}_{0}=35$ K with saturation value ${ {SS}}( {T} . The proposed model adequately describes the experimental data of SS(T) from 300 down to 4 K using $ {k}_{ {B}} {T}_{0} \simeq 3$ meV for the width of the exponential tail and can also accurately describe ${ {SS}}( {I}_{ {D}})$ within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and the design of cryogenic circuits.