STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

A design methodology for LLC resonant converters based on inspection of resonant tank currents.

Abstract: This paper presents a simple and accurate design methodology for LLC resonant converters, based on a semi- empirical approach to model steady-state operation in the "be- low-resonance" region. This model is framed in a design strategy that aims to design a converter capable of operating with soft-switching in the specified input voltage range with a load ranging from zero up to the maximum specified level.

Simple and efficient modeling of EPROM writing

Abstract: A simple and efficient model for first-order simulation of the writing of n-channel erasable programmable ROM (EPROM) cells is presented. It allows the current injected into the gate insulator of the cell transistor to be calculated, accounting (at first order) both for the nonMaxwellian form of the electron energy distribution and for the nonlocal nature of carrier heating. The model is implemented as a postprocessor of a two-dimensional device simulator, and it is validated by means of a comparison with experimental data obtained with devices with effective channel lengths ranging from 1.4 to 0.5 mu m. >

Microprocessor having an on-chip CPU fetching a debugging routine from a memory in an external debugging device in response to a control signal received through a debugging port

Abstract: There is disclosed a computer system including a microprocessor on an integrated circuit chip comprising an on-chip CPU and a debugging port connected to a communication bus on the integrated circuit and to an external debugging computer device. The external debugging device is operable to transmit control signals through the debugging port: a) to stop execution by the CPU of instructions obtained from a first on-chip memory; b) to provide from a second memory associated with the external debugging computer device a debugging routine to be executed by the CPU; and c) to restart operation of the CPU after the routine with execution of instructions from an address determined by the external debugging device. The on-chip CPU is operable with code in the first memory which is independent of the debugging routine. A method of operating such a computer system with an external debugging device is also disclosed.

Trench MOS-gated device with a minimum number of masks

Abstract: A low-voltage high-current discrete insulated-gate field-effect transistor which is made by a very economical process with two silicon etches. A buried poly gate gates conduction along a trench sidewall. The channel is provided by the residuum of an epi layer, and the source diffusion is provided by an unmasked implant which is screened only by various grown oxides.

Investigation of the underfill delamination and cracking in flip-chip modules under temperature cyclic loading

Abstract: In this paper, stress singularity in electronic packaging is described and three general cases are summarized. The characteristics of each stress singularity are briefed. In order to predict the likelihood of delamination at a bimaterial wedge, where two interfaces are involved, a criterion is proposed and the corresponding parameters are defined. The propagation of a crack inside a homogeneous material with the effects of delamination and stress singularity is predicted by the maximum hoop stress criterion. The proposed criteria are adopted in the analysis of a flip-chip with underfill under thermal cyclic loading. A finite element (FE) model for the package is built and the proper procedures in processing FE data are described. The proposed criterion can correctly predict the interface where delamination is more likely to occur. It can be seen that the opening stress intensity factor along the interface (or peeling stress) plays a very important role in causing interfacial failure. The analytical results are compared with experimental ones and good agreement is found. The effects of delamination and cracking inside the package on the solder balls are also mentioned. Further investigation into the fatigue model of the underfilled solder ball is discussed.