STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

Abstract: A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-?m 2.5-V standard I/O FETs in a 0.13-?m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.

LED driver circuit and method

Abstract: An LED driver circuit and method are disclosed where an array of light emitting diodes have a transistor connected to each respective array of light emitting diodes. A PWM controller has an input for receiving a voltage reference and an output connected to selected transistors for driving selected transistors and setting a PWM duty cycle for the selected arrays of light emitting diodes to determine the brightness of selected light emitting diodes. An oscillator is connected to the PWM controller for driving the PWM controller.

Precipitation behavior and its effect on strengthening of an HSLA-Nb/ti steel

Abstract: The precipitation behavior of a commercial high-strength low-alloy (HSLA) steel microalloyed with 0.086 wt pct Nb and 0.047 wt pct Ti has been investigated using transmission electron microscopy (TEM) and mechanical testing. The emphasis of this study is to compare an industrially hot-rolled steel and samples from a laboratory hot torsion machine simulation. From TEM observations, the Ti and Nb containing precipitates could be grouped according to their size and shape. The precipitates in order of size were found to be cubic TiN particles with sizes in the range of 1 µm, grain boundary precipitates with diameters of approximately 10 nm, and very fine spherical or needle-shaped precipitates with sizes on the order of 1 nm. The needlelike precipitates were found on dislocations in ferrite and constituted the dominant population in terms of density. Thus, they appear to be responsible for the precipitation strengthening observed in this steel. Aging tests were carried out at 650°C to evaluate the precipitate strengthening kinetics in detail. The strengthening mechanisms can be described with a nonlinear superposition of dislocation and precipitation hardening. The mechanical properties of torsion-simulated material and as-coiled industrial material are similar; however, there are some microstructural differences that can be attributed to the somewhat different processing routes in the laboratory as compared to hot strip rolling.

Method of managing fails in a non-volatile memory device and relative memory device

Abstract: A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. Each block including at least one failed cell in the first subset is located during a test on wafer of the non-volatile memory device. Each block is marked as bad, and a bad block address table of respective codes is stored in a non-volatile memory buffer. At power-on, the bad block address table is copied from the non-volatile memory buffer to the random access memory. A block of memory cells of the first subset is verified as bad by looking up the bad block address table, and if a block is bad, then remapping access to a corresponding block of redundancy cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.