STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

A Bluetooth radio in 0.18-/spl mu/m CMOS

Abstract: This paper describes the results of an implementation of a Bluetooth radio in a 0.18-/spl mu/m CMOS process. A low-IF image-reject conversion architecture is used for the receiver. The transmitter uses direct IQ-upconversion. The VCO runs at 4.8-5.0 GHz, thus facilitating the generation of 0/spl deg/ and 90/spl deg/ signals for both the receiver and transmitter. By using an inductor-less LNA and the extensive use of mismatch simulations, the smallest silicon area for a Bluetooth radio implementation so far can be reached: 5.5 mm/sup 2/. The transceiver consumes 30 mA in receive mode and 35 mA in transmit mode from a 2.5 to 3.0-V power supply. As the radio operates on the same die as baseband and SW, the crosstalk-on-silicon is an important issue. This crosstalk problem was taken into consideration from the start of the project. Sensitivity was measured at -82 dBm.

Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm 2 6T-SRAM bitcell

Abstract: In this paper, we report on FD-SOI with high-k and single metal gate as a possible candidate for the 32 nm LOP and LSTP nodes. Good Ion/Ioff performance for nMOS and pMOS transistors in the ultra-low-leakage regime (Ioff=6.6 pA/μm) are presented. In addition co-integration of high voltage devices with EOT 29A/Vdd 1.8 V are made. For the first time, the functionality of 0.248 μm and 0.179 μm2 6T-SRAM bit-cells is demonstrated on FDSOI technology with a high-k/metal gate stack.

Electrical analysis of external mechanical stress effects in short channel MOSFETs on (0 0 1) silicon

Abstract: This paper presents an electrical analysis of external mechanical stress effects on devices characteristics for long and short channel MOSFETs in advanced 0.13 μm technology. Similar bulk and SOI generations for nMOS and pMOS devices are studied. By applying external calibrated stress we measure piezoresistive effects and compare small and long transistors electrical responses. Main results are that the threshold voltage (Vt) variations were shown negligible whereas mobility dependence with stress was the most significant effect. After the parasitic series resistance (Rsd) correction on short devices, we extracted comparable piezoresistive coefficients on short and long devices indicating that 2D or local effects can be neglected in all cases. Comparison bulk/SOI showed slightly higher piezoresistive coefficients for SOI. Finally, measurement errors were estimated.

New Mechanism of Body Charging in Partially Depleted SOI-MOSFETs with Ultra-thin Gate Oxides

Abstract: The aggressive scaling of the gate oxide leads to direct gate tunneling current, which affects the floatingbody effects in partially-depleted SOI MOSFETs. Experiments and simulations show that the gate-to-body current charges the body causing an unexpected ‘kink’ effect to occur at low drain voltage. This kink results in a second peak of transconductance, whose time-dependent behavior and practical consequences are investigated.