Institution
STMicroelectronics
Company•Geneva, Switzerland•
About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.
Topics: Transistor, Signal, Integrated circuit, CMOS, Layer (electronics)
Papers published on a yearly basis
Papers
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TL;DR: In this article, the evolution of silicon cryoetching is reported from its very first introduction by a Japanese team to today's advanced technologies, and the main defects encountered in the process are presented and discussed.
Abstract: The evolution of silicon cryoetching is reported in this topical review, from its very first introduction by a Japanese team to today's advanced technologies. The main advances in terms of the performance and comprehension of the mechanisms are chronologically presented. After presenting the principle of silicon cryoetching, the main defects encountered in cryoetching (such as undercut, bowing and crystal orientation dependent etching) are presented and discussed. Mechanisms involved in SiOxFy passivation layer growth in standard cryoetching are investigated through several in situ characterization experiments. The STiGer process and alternative cryoetching processes for high-aspect-ratio structures are also proposed to enhance the process robustness. The over-passivation regime, which can provide self-organized columnar microstructures, is presented and discussed. Finally, advanced technologies, such as the cryoetching of sub-20 nm features and porous OSG low-k cryoetching, are described.
217 citations
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01 Jan 2001TL;DR: This chapter will describe evolutionary algorithms that seem to respond to the characteristics required by soft computing, both with regard to versatility and to the efficiency and goodness of the results obtained.
Abstract: As pointed out in the previous chapters, both fuzzy logic and neural networks imply optimization processes. For fuzzy logic in particular, optimization algorithms are needed that will allow determinations of the number of rules, the number of fuzzy sets and their position in the universe of discourse to be based on optimum criteria instead of on empirical techniques. This process generally involves a large number of variables and thus requires particularly efficient optimization algorithms. Similarly, in the field of neural networks, what can be of considerable use are optimization algorithms capable of finding the global minimum of a function with many variables, in order to overcome the intrinsic limitations inherent in learning algorithms based on the gradient technique. Therefore, this chapter will describe evolutionary algorithms that seem to respond to the characteristics required by soft computing, both with regard to versatility and to the efficiency and goodness of the results obtained. Genetic algorithms have proved to be a valid procedure for global optimization, applicable in very many sectors of engineering [10–15]. Ease of implementation and the potentiality inherent in an evolutionist approach make genetic algorithms a powerful optimization tool for non-convex functions. The genetic algorithms (GA) represent a new optimization procedure based on Darwin’s natural evolution principle. Adopting this analogy, inside a population in continuous evolution, the individual who best adapts to environmental constraints corresponds to the optimal solution of the problem to be solved.
216 citations
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TL;DR: In this article, an optimized strategy for designing charge pumps with minimum power consumption is presented, which allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency.
Abstract: In this paper, an optimized strategy for designing charge pumps with minimum power consumption is presented. The approach allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency. Capacitor value is then set to provide the current capability required. This approach was analytically developed and validated through simulations and experimental measurements on 0.35-/spl mu/m EEPROM CMOS technology. This approach was then compared with one which minimized the silicon area and it was shown that only a small increase in area is needed to minimize power consumption.
214 citations
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TL;DR: In this paper, the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m.
Abstract: This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).
210 citations
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20 Jan 1999TL;DR: In this article, a plurality of capacitance sensing cells are arranged in a row/column array top to cooperate with a fingertip and produce an output signal that controls the movement of a cursor/pointer across a display screen.
Abstract: A plurality N of capacitance sensing cells are arranged in a row/column array top to cooperate with a fingertip and produce an output signal that controls the movement of a cursor/pointer across a display screen. The output of each individual sensing cell is connected to the corresponding individual node of a resistor array that has N nodes arranged in a similar row/column array. A centroid output of the resistor nodes in row configuration provides an output signal for control of cursor movement in a row direction. A centroid output of the resistor nodes in column configuration provides an output signal for control of cursor movement in an orthogonal column direction. A mass signal output of the row/column resistor mode array provides a switch on/off signal.
210 citations
Authors
Showing all 17185 results
Name | H-index | Papers | Citations |
---|---|---|---|
Bharat Bhushan | 116 | 1276 | 62506 |
Albert Polman | 97 | 445 | 42985 |
G. Pessina | 84 | 828 | 30807 |
Andrea Santangelo | 83 | 886 | 29019 |
Paolo Mattavelli | 74 | 482 | 19926 |
Daniele Ielmini | 68 | 367 | 16443 |
Jean-François Carpentier | 62 | 459 | 14271 |
Robert Henderson | 58 | 440 | 13189 |
Bruce B. Doris | 56 | 604 | 12366 |
Renato Longhi | 55 | 177 | 8644 |
Aldo Romani | 54 | 425 | 11513 |
Paul Muralt | 54 | 344 | 12694 |
Enrico Zanoni | 53 | 705 | 13926 |
Gaudenzio Meneghesso | 51 | 703 | 12567 |
Franco Zappa | 50 | 274 | 9211 |