scispace - formally typeset
Search or ask a question
Institution

STMicroelectronics

CompanyGeneva, Switzerland
About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.


Papers
More filters
Journal ArticleDOI
TL;DR: This paper discusses the design of 77-106 GHz Colpitts VCOs fabricated in two generations of SiGe BiCMOS technology, with MOS and HBT varactors, and with integrated inductors, based on a study of the optimal biasing conditions for minimum phase noise.
Abstract: This paper discusses the design of 77-106 GHz Colpitts VCOs fabricated in two generations of SiGe BiCMOS technology, with MOS and HBT varactors, and with integrated inductors. Based on a study of the optimal biasing conditions for minimum phase noise, it is shown that VCOs can be used to monitor the mm-wave noise performance of SiGe HBTs. Measurements show a 106 GHz VCO operating from 2.5 V with phase noise of -101.3 dBc/Hz at 1 MHz offset, which delivers +2.5 dBm of differential output power at 25degC, with operation verified up to 125degC. A BiCMOS VCO with a differential MOS-HBT cascode output buffer using 130 nm MOSFETs delivers +10.5 dBm of output power at 87 GHz.

65 citations

Book ChapterDOI
23 Jun 2009
TL;DR: In this paper, a combination of compositional modeling, model checking, and Markov process theory is used to compute performance quantities directly on industrial, functionally verified globally asynchronous, locally synchronous systems.
Abstract: Systems and Networks on Chips (NoCs) are a prime design focus of many hardware manufacturers. In addition to functional verification, which is a difficult necessity, the chip designers are facing extremely demanding performance prediction challenges, such as the need to estimate the latency of memory accesses over the NoC. This paper attacks this problem in the setting of designing globally asynchronous, locally synchronous systems (GALS). We describe foundations and applications of a combination of compositional modeling, model checking, and Markov process theory, to arrive at a viable approach to compute performance quantities directly on industrial, functionally verified GALS models.

65 citations

Patent
30 Sep 1993
TL;DR: In this paper, a plurality of elementary Hall-effect sensors are integrated side by side and aligned in a direction perpendicular to the zeroing field component and to the current flowing through the elementary sensors.
Abstract: For detecting the position of a magnetic element having a field component zeroing in at least one point in space, typically in a plane, a plurality of elementary Hall-effect sensors are integrated side by side and aligned in a direction perpendicular to the zeroing field component and to the current flowing through the elementary sensors. The elementary sensor generating a zero output voltage therefore indicates the zero position of the field component and consequently the position of the magnetic element with respect to the position sensor, so that The outputs of the elementary sensors provide a quantized numeric code indicating the position of the magnetic element.

64 citations

Patent
25 Aug 1998
TL;DR: In this article, a bus interface unit includes a random-access transaction buffer and at least one pointer queue, and a method is provided for processing requested bus transactions, where the bus interfaces unit determines if a requested transaction is a combinable write transaction.
Abstract: A bus interface unit includes a random-access transaction buffer and at least one pointer queue. The transaction buffer stores entries for both in-order transactions and combinable write transactions, and the pointer queue stores pointers to the buffer entries for in-order transactions so as to order the in-order transactions. When a received combinable write transaction has a writing address that falls within the address range of a stored combinable write transactions, the received transaction is merged with the stored transaction. Additionally, a method is provided for processing requested bus transactions. The bus interface unit determines if a requested transaction is a combinable write transaction. If not, address and data information for the requested transaction is loaded into an empty entry in a random-access buffer, and a pointer to that buffer entry is placed in a pointer queue. Alternatively, if the requested transaction is a combinable write transaction, the bus interface unit determines if the transaction's write address falls within the address range of a stored combinable write transaction. If so, the requested transaction is merged with the stored transaction. In a preferred embodiment, if the write address does not fall within the address range of any stored combinable write transaction, the data information for the requested transaction is loaded into an empty entry in the random-access buffer.

64 citations

Journal ArticleDOI
TL;DR: Growth of single crystal 3C-SiC films on large area off-axis (111) Si substrate by chemical vapour deposition technique is reported in this paper, which shows an extremely flat surface and interface, stimulating further interest for electrical and mechanical device applications even if a strong bow, due to the strain induced by the growth process, is observed.

64 citations


Authors

Showing all 17185 results

NameH-indexPapersCitations
Bharat Bhushan116127662506
Albert Polman9744542985
G. Pessina8482830807
Andrea Santangelo8388629019
Paolo Mattavelli7448219926
Daniele Ielmini6836716443
Jean-François Carpentier6245914271
Robert Henderson5844013189
Bruce B. Doris5660412366
Renato Longhi551778644
Aldo Romani5442511513
Paul Muralt5434412694
Enrico Zanoni5370513926
Gaudenzio Meneghesso5170312567
Franco Zappa502749211
Network Information
Related Institutions (5)
Intel
68.8K papers, 1.6M citations

92% related

Motorola
38.2K papers, 968.7K citations

91% related

Samsung
163.6K papers, 2M citations

90% related

NEC
57.6K papers, 835.9K citations

89% related

Toshiba
83.6K papers, 1M citations

89% related

Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
202225
2021560
2020798
2019952
2018948
2017781