STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Implementation of a CMOS LNA plus mixer for GPS applications with no external components

Abstract: A fully differential 0.35-/spl mu/m CMOS LNA plus mixer, for GPS applications, using no external component apart from an input balun, has been realized. The LNA makes use of an inductively degenerated input stage and a resonant LC load, featuring 12% frequency tuning, accomplished by a MOS varactor. The mixer is a Gilbert cell type in which an NMOS and a PMOS differential pair, shunt together, realize the input stage. This topology allows one to save power for given mixer gain and linearity. The front-end measured performances are: 40-dB gain, 3.8-dB NF, -25.5-dBm IIP3, 1.3-GHz input frequency, 140-MHz output frequency, with 8 mA from a 2.8-V supply.

A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

Abstract: Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human–Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from −1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range −40 °C to 120 °C exploiting −1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors with comparable performance, including those implemented in 28 nm technology, our platform provides 1.4× to 3.7× better energy efficiency.

Multi-gate devices for the 32nm technology node and beyond

Abstract: Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed Apart from the benefits, some technological challenges will be addressed

Scalable Video Coding for IPTV Services

Abstract: Scenarios for the use of the recently approved scalable video coding (SVC) extension of H.264/MPEG4-AVC in IPTV services are presented. For that, a brief technical overview of SVC when deployed in IPTV services is provided. The coding efficiency of the various scalability types of SVC is demonstrated followed by an analysis of the complexity of the various SVC tools. Based on this technical characterization, it is described how the different SVC features such as efficient methods for graceful degradation, bit rate adaptation, and format adaptation, can be mapped to application requirements of IPTV services. It is discussed how such mappings can lead to improved content portability, management and distribution as well as an improved management of access network throughput resulting in better quality of service and experience for the users of IPTV services.

Isolation between power supplies of an analog-digital circuit

Abstract: The present invention relates to a composite integrated circuit including at least one well that separates analog and digital blocks of the circuit, this well being connected to a first terminal of a power supply of biasing of one of the two blocks, and being of type opposite to that of the circuit substrate, and a resistor being interposed on the well biasing link.