STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Hyperdimensional Computing for Blind and One-Shot Classification of EEG Error-Related Potentials

Abstract: The mathematical properties of high-dimensional (HD) spaces show remarkable agreement with behaviors controlled by the brain. Computing with HD vectors, referred to as “hypervectors,” is a brain-inspired alternative to computing with numbers. HD computing is characterized by generality, scalability, robustness, and fast learning, making it a prime candidate for utilization in application domains such as brain–computer interfaces. We describe the use of HD computing to classify electroencephalography (EEG) error-related potentials for noninvasive brain–computer interfaces. Our algorithm naturally encodes neural activity recorded from 64 EEG electrodes to a single temporal–spatial hypervector without requiring any electrode selection process. This hypervector represents the event of interest, can be analyzed to identify the most discriminative electrodes, and is used for recognition of the subject’s intentions. Using the full set of training trials, HD computing achieves on average 5% higher single-trial classification accuracy compared to a conventional machine learning method on this task (74.5% vs. 69.5%) and offers further advantages: (1) Our algorithm learns fast: using only 34% of training trials it achieves an average accuracy of 70.5%, surpassing the conventional method. (2) Conventional method requires prior domain expert knowledge, or a separate process, to carefully select a subset of electrodes for a subsequent preprocessor and classifier, whereas our algorithm blindly uses all 64 electrodes, tolerates noises in data, and the resulting hypervector is intrinsically clustered into HD space; in addition, most preprocessing of the electrode signal can be eliminated while maintaining an average accuracy of 71.7%.

Recent progress in Silicon Photonics R&D and manufacturing on 300mm wafer platform

Abstract: A low cost 28Gbits/s Silicon Photonics platform using 300mm SOI wafers is demonstrated. Process, 3D integration of Electronic and Photonic ICs, device performance, circuit results and low cost packaging are discussed.

Multicast with cache (Mcache): an adaptive zero-delay video-on-demand service

Abstract: A closed-loop (demand-driven) approach toward video-on-demand services, called multicast cache (Mcache), is discussed. Servers use multicast to reduce their bandwidth usage by allowing multiple requests to be served with a single data stream. However, this requires clients to delay receiving the movie until the multicast starts. Using regional cache servers deployed over many strategic locations, Mcache can remove the initial playout delays of clients in multicast-based video streaming. While requests are batched together for a multicast, clients can receive the prefix of a requested movie clip from caches located in their own regions. The multicast containing the later portion of the movie can wait until the prefix is played out. While this use of regional caches has been proposed previously, the novelty of our scheme lies in that the requests coming after the multicast starts can still be batched together to be served by multicast patches without any playout delays. The use of patches was proposed before, but they are used either with unicast or with playout delays. Mcache effectively hires the idea of a multicast patch with caches to provide a truly adaptive video-on demand service whose bandwidth usage is up to par with the best known open-loop schemes under high request rates while using only minimal bandwidth under low request rates. In addition, efficient use of multicast and caches removes the need for a priori knowledge of client disk storage requirements which some of the existing schemes assume. This makes Mcache ideal for the current heterogeneous Internet environments where those parameters are hard to predict. We further propose the Segmented Mcache (SMcache) scheme which is a generalized and improved version of Mcache where the clip is partitioned into several segments in order to preserve the advantages of the original Mcache scheme with nearly the same server bandwidth requirement as the open loop schemes under high request rates.

Method of reconstructing an analog signal, particularly in digital telephony applications, and a circuit device implementing the method

Abstract: A method of reconstructing an analog signal, particularly for digital telephony, comprises a first step of digital-to-analog conversion, wherein a first reconstruction of the analog signal is provided by introducing a distortion component into the frequency spectrum whose amplitude decreases with the signal frequency, and a second step of filtering carried out by means of a reconstruction filter provided with integrators and having a cut-off frequency F t . That attenuating distortion component is utilized instead of one of the integrators in the reconstruction filter, to afford a reduction of the overall design of the circuit device operating in accordance with this method, and bring about, as a result, decreased occupation of the integrated circuit and power dissipation.

Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

Abstract: Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed