STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Fully substrate-isolated FinFET transistor

Abstract: Channel-to-substrate leakage in a FinFET device can be prevented by inserting an insulating layer between the semiconducting channel (fin) and the substrate Similarly, source/drain-to-substrate leakage in a FinFET device can be prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate The insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage If an array of semiconducting fins is made up of a multi-layer stack, the bottom material can be removed thus yielding a fin array that is suspended above the silicon surface A resulting gap underneath the remaining top fin material can then be filled in with oxide to better support the fins and to isolate the array of fins from the substrate The resulting FinFET device is fully substrate-isolated in both the gate region and the source/drain regions

Apparatus and method for contacting a conductive layer

Abstract: A structure and method for creating a contact between a conductive layer and a pad for dissipating electrostatic charges comprising the steps of, forming a pad and a composite insulating layer between and over conductive plates on a substrate, wherein the insulating layer isolates and protects the conductive plates and pad from damage, the insulating layer comprising a dielectric region underlying a conductive layer. A passivation layer is formed over at least a portion of the conductive layer and a photoresist is patterned over at least a portion of the passivation. An opening is etched through the passivation and the insulating layers, wherein the photoresist and the conductive layer serve as masks. Finally, a conductive material is deposited in the opening to form an electrical contact between the pad and the conductive layer.

A controller for implementing scan testing

Abstract: A test access port controller is provided for implementing scan testing with a chain of scan latches on an integrated circuit. The test access port controller can implement a structural test or a performance test. Selection between the two types of test is achieved through logic circuitry of the test access port controller. An integrated circuit and a test system are also provided.

An evolutionary algorithm-based approach to robust analog circuit design using constrained multi-objective optimization

Abstract: The increasing complexity of circuit design needs to be managed with appropriate optimization algorithms and accurate statistical description of design models in order to reach the design specifics, guaranteeing ''zero defects''. In the Design for Yield open problems are the design of effective optimization algorithms and statistical analysis for yield design, which require time consuming techniques. New methods have to balance accuracy, robustness and computational effort. Typical analog integrated circuit optimization problems are computationally hard and require the handling of multiple, conflicting, and non-commensurate objectives having strong nonlinear interdependence. This paper tackles the problem by evolutionary algorithms to produce tradeoff solutions on the Pareto Front. In this research work Integrated Circuit (IC) design has been formulated as a constrained multi-objective optimization problem defined in a mixed integer/discrete/continuous domain. The following real-life circuits, RF Low Noise Amplifier, LeapFrog Filter, and Ultra Wideband LNA, were selected as test bed. The proposed algorithm, A-NSGAII, was shown to produce acceptable and robust solutions in the tested applications, where state-of-art algorithms and circuit designers failed. The results show significant improvement in all the chosen IC design problems.

Motion estimation process and system

Abstract: A motion estimation process in video signals organized in successive frames divided into macroblocks that is carried out by the identification of motion vectors. In a first identification phase, starting from a current motion vector, a best motion vector predictor is identified, chosen from a set of candidates. The best predictor thus identified is then subjected to a second refining phase. The aforesaid set of candidates is identified by selecting vectors belonging to macroblocks close to the current vector within the current frame and the preceding frame. Preferably, the refining phase comprises the definition of a grid of n points centered on the central position to which the best motion vector points and the distance of the points of the grid from the center is defined as a function of the matching error typically consisting of an SAD function, defined in the first identification phase. Application to the IPB and APM operating modes of the H.263+ video standard is envisaged.