STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Architecture of a phase-change nonvolatile memory array

Abstract: The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

A 2.4 GHz Interferer-Resilient Wake-Up Receiver Using A Dual-IF Multi-Stage N-Path Architecture

Abstract: A 2.4 GHz interferer-resilient wake-up receiver for ultra-low power wireless sensor nodes uses an uncertain-IF dual-conversion topology, combining a distributed multi-stage N-path filtering technique with an unlocked low-Q resonator-referred local oscillator. This structure provides narrow-band selectivity and strong immunity against interferers, while avoiding expensive external resonant components such as BAW resonators or crystals. The 65 nm CMOS receiver prototype provides a sensitivity of −97 dBm and a carrier-to-interferer ratio better than −27 dB at 5 MHz offset, for a data rate of 10 kb/s at a 10−3 bit error rate, while consuming 99 $\mu \text{W}$ from a 0.5 V voltage supply under continuous operation.

Integrated circuit package with battery housing

Abstract: An integrated circuit, typically a random access memory, is housed in a package (14). In the application associated with the integrated circuit it is desired to maintain the data states stored in the memory even when the normal supply voltage is disconnected from the package (14). Batteries (24, 26) are secured in recesses (20, 22) within a structure (12) which is connected to the integrated circuit package (14). A top spring clip (100) is provided to securely hold the batteries (24, 26) within the recesses (20, 22) and forms a common conductor in contact with the upper terminal of both batteries. A bottom spring clip (74, 76) is provided for each of the recesses (20, 22) to form separate conductors in contact with the lower terminal of each battery. The batteries can be readily inserted and removed over lips (64, 70) in the recess (20, 22).

Gold Nanoparticle/Polymer Interfaces: All Atom Structures from Molecular Dynamics Simulations

Abstract: Molecular dynamics simulations have been performed to obtain detailed all-atom models of the interface between polystyrene (PS) and gold nanoparticles. Considering their relevance in the memory technology, systems containing gold nanoparticle included in PS polymer melts also in the presence of 8-hydroxyquinoline (8-HQ) molecules have been studied. Four different systems, including a coated or a noncoated nanoparticle, have been compared. Calculated radial density profiles show that the presence of noncoated nanoparticles in a polymer melt causes an ordering of polymer chains. A similar ordering behavior is found for the 8-HQ molecule. In the presence of a coated gold nanoparticle, calculated radial density profiles show much less order. When 8-HQ is present, this molecule is closer to the nanoparticle surface and when in contact with a coated nanoparticle it shows a partial penetration into the thiols layer. The molecular description obtained from simulations supports some of the hypothesis made on the b...

Digital Deadbeat Control Tuning for dc-dc Converters Using Error Correlation

Abstract: This paper proposes a simple tuning algorithm for digital deadbeat control based on error correlation By injecting a square wave reference input and calculating the correlation of the control error, a gain correction for deadbeat control is obtained The proposed tuning algorithm is successfully applied also in predictive algorithms which use disturbance observers for the compensation of input voltage variations and any other source of errors, such as dead-times, parameter and model mismatches The proposed solution is simple, it requires short tuning time, it is suitable for different dc-dc converter topologies and it seems to be compliant with the cost/complexity constraint of integrated digital ICs Simulation and experimental results on synchronous buck converters confirm the properties of the proposed solution