STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Digital Deadbeat Control Tuning for dc-dc Converters Using Error Correlation

Abstract: This paper proposes a simple tuning algorithm for digital deadbeat control based on error correlation By injecting a square wave reference input and calculating the correlation of the control error, a gain correction for deadbeat control is obtained The proposed tuning algorithm is successfully applied also in predictive algorithms which use disturbance observers for the compensation of input voltage variations and any other source of errors, such as dead-times, parameter and model mismatches The proposed solution is simple, it requires short tuning time, it is suitable for different dc-dc converter topologies and it seems to be compliant with the cost/complexity constraint of integrated digital ICs Simulation and experimental results on synchronous buck converters confirm the properties of the proposed solution

Displacement detection device for a portable apparatus

Abstract: In a displacement detection device, an acceleration sensor generates at least a first acceleration signal relating to an axis of detection, and a displacement detection circuit is connected to the acceleration sensor has a comparator stage for comparing the acceleration signal with a programmable acceleration threshold and generates a displacement-detection signal. A high-pass filter is arranged between the acceleration sensor and the comparator stage so as to reduce a DC component of the acceleration signal. The cut-off frequency of the high-pass filter is modified according to the type of displacements that are to be detected.

High frequency characterization and modeling of high density TSV in 3D integrated circuits

Abstract: High frequency characterization and modeling of Through Silicon Vias (TSVs) for new 3D chip staking are presented in this paper. Works focus on high density TSVs, up to 106 cm−2, with pitch below 10 µm and aggressive wafer thinning to maintain TSV aspect ratio in a range between 5 and 10. Equivalent electrical RLCG models of TSVs with height of 15 µm and diameter of 3 µm are extracted up to 20 GHz. It is shown that values extracted for components are directly related to design and material characteristics used to process 3D TSVs.

MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures

Abstract: Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.

Process for manufacturing semiconductor packages comprising an integrated circuit

Abstract: A process for manufacturing semiconductor packages comprising, respectively, a substrate, a chip which forms an integrated circuit and is attached to one region of the substrate, electrical connection means connecting the chip to a group of external electrical connection regions lying on one face of the substrate, as well as an encapsulation encasement. The process consists in producing, in a matrix configuration, a multiplicity of groups of connection regions (104a) on a common substrate plate (102), corresponding to as many chip attachment regions (109), in attaching a chip (103) to each attachment region (109) of the common substrate plate, in electrically connecting each chip (103) to the associated electrical connection regions (104a), so as to obtain an assembly (111) consisting of the substrate plate and the connected chips. The process consists, in a second step, in placing this assembly (111) in a mold (112) and in injecting an encasement material (106) into the mold so as to obtain, in a single molding operation, a parallelepipedal block (117) and then, in a subsequent step, in cutting the said parallelepipedal block (117) through its thickness into units, each constituting a semiconductor package.