STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Signal processing circuit to implement a Viterbi algorithm

Abstract: To carry out the processing operations relating to the implementation of a Viterbi algorithm, an integrated circuit comprising a processor and a coprocessor is made. The coprocessor is constructed so as to carry out operations of accumulation, comparison and selection in order to limit or reduce the work of a processor that would have to carry out these operations. By judiciously choosing the structure of the coprocessor, it is possible to make this co-processor sufficiently programmable so that it is suited to various situations of implementation of the Viterbi algorithm.

Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs

Abstract: Extensive investigation of the low-frequency noise in n-channel and p-channel MOSFETs, with high-k gate stack and channel length varying from 1.8 μm down to 26.4 nm, has been carried out. The results demonstrate that the carrier number fluctuation with correlated mobility fluctuations describes accurately and continuously the 1/f noise for all operation regions, i.e. from weak to strong inversion and from linear to saturation. It has been found that the product of the Coulomb scattering coefficient and the effective carrier mobility α sc μ eff is constant over a wide range of the drain current due to the interplay of the Coulomb scattering coefficient αsc and the effective carrier mobility μeff variations. In addition, a non-linear increase in the square root of the input gate voltage noise with the gate voltage overdrive was observed explained by the surface roughness scattering. The overall results lead to an analytical expression for the 1/f noise model, enabling to predict the noise level of a transistor with any channel dimensions using its transfer characteristic. This finding makes the noise model suitable for circuit simulation tools.

40-mm/sup 2/ 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory

Abstract: This paper presents a 3-V-only 64-Mb 4-level-cell (2-b/cell) NOR-type channel-hot-electron (CHE) programmed flash memory fabricated in 0.18-/spl mu/m shallow-trench isolation CMOS technology. The device (die size 40 mm/sup 2/) is organized in 64 1-Mb sectors. Hierarchical column and row decoding ensures complete isolation between different sectors during any operation, thereby increasing device reliability while still providing layout area optimization. Staircase gate-voltage programming is used to achieve narrow threshold-voltage distributions. The same program throughput as for bilevel CHE-programmed memories is obtained, thanks to parallel programming. A mixed balanced/unbalanced sensing approach allows efficient use of the available threshold window. Asynchronous (130-ns access time) and burst-mode (up to 50-MHz data rate) reading is possible. Both column and row redundancy is provided to ensure extended failure coverage. Error correction code techniques, correcting 1 failed over 32 data cells, are also integrated.

Monitoring of current in an inductive load, PWM driven through a bridge stage

Abstract: Monitoring of current flowing through an inductive load driven through a bridge power stage in a PWM mode, comprises sampling the signal output by a sensing amplifier with a Sample & Hold circuit including a sampling switch and a storing capacitor The average value of the current in the load is monitored by sampling at a half way point of an active driving phase and at a half way point of a current recirculation phase by closing the switch with a synchronizing pulse that coincides with the half way points of these phases of operation The monitoring uses a pair of complementary periodic reference signals and uses a sensing amplifier to amplify the signal existing on a current sensing resistor functionally connected in series with the load This produces an amplified signal representative of the current in the load to be fed to an input of an error amplifier driving a power amplifier of the bridge stage The synchronizing pulse is generated in coincidence with the peak and with the virtual zero crossing of the two reference periodic signals, out of phase from one another by 180 degrees A two-input logic AND gate, combining the synchronizing pulse and a masking signal of a preestablished duration generated at every switching of the bridge stage may also be employed

Altitude and Underground Real-Time SER Characterization of CMOS 65 nm SRAM

Abstract: We report real-time SER characterization of CMOS 65 nm SRAM memories in both altitude and underground environments. Neutron and alpha-particle SERs are compared with data obtained from accelerated tests and values previously measured for CMOS 130 nm technology.