STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs

Abstract: We present measurements for the standard deviation of the threshold voltage in n- and p-channel MOSFETs from the 45-nm low-power platform of STMicroelectronics. The measurements are compared with 3-D statistical simulations carried out with the Glasgow ldquoatomisticrdquo device simulator, considering random discrete dopants, line edge roughness, and the polysilicon granularity of the gate electrode. It was found that the surface potential pinning at the poly-Si grain boundaries (GBs), which is important for explaining the magnitude of the statistical variability of the n-channel MOSFETs, plays a negligible role in the p-channel case. First-principle simulation of low-angle silicon GBs is performed in order to explain the systematically observed differences in the threshold voltage standard deviation of the measured n- and p-channel MOSFETs.

Semiconductor contact via structure and method

Abstract: A contact opening through an insulating layer is filled with metal and etched back to form a metal plug within the opening. A metal interconnect line can then be formed over the contact, and makes electrical contact with the metal plug. Since the contact opening is filled by the metal plug, it is not necessary for the metal signal line to have a widened portion in order to ensure enclosure.

A conservative approach to systemc parallelization

Abstract: SystemC has become a very popular language for the modeling of System-On-Chip (SoC) devices. However, due to the ever increasing complexity of SoC designs, the ever longer simulation times affect SoC exploration potential and time-to-market. We investigate the use of parallel computing to exploit the inherent concurrent execution of the hardware components, and thus to speed up the simulation of complex SoC’s. A parallel SystemC prototype based on the open source OSCI kernel is introduced and preliminary results are discussed.

Method for forming controlled voids in interlevel dielectric

Abstract: A method of forming a thick interlevel dielectric layer containing sealed voids, formed in a controlled manner, over a substantially planar surface in semiconductor device structure, and the semiconductor structure formed according to such a method. The sealed voids are used to reduce interlevel capacitance. A plurality of metal signal lines are formed over a globally planarized insulator. A thick layer of first conformal interlevel dielectric is deposited over the metal signal lines and over the intermetal spacings formed between the metal signal lines. Because of the thickness, flow properties, and manner of deposition of the interlevel dielectric and the aspect ratio the intermetal spacings, voids are formed in the first conformal interlevel dielectric, in the intermetal spacings. This interlevel dielectric is then etched or polished back to the desired thickness, which exposes the voids in the wider intermetal spacings, but does not expose voids in the narrower intermetal spacings. An etchback may be chosen so that all voids are exposed. The exposed voids are filled with a flowable dielectric which can be then etched back to leave the flowable dielectric in the exposed voids. A second conformal interlevel dielectric layer is formed over the first conformal interlevel dielectric to further bury the sealed voids, insuring that they do not get exposed in further process steps. The second conformal interlevel dielectric may be formed in a thin layer to allow the flowable dielectric to remain near the top of the interlevel dielectric structure to reduce the possibility of poisoned vias.

Integrated circuit comprising a transistor and a capacitor, and fabrication method

Abstract: An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.