STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction

Abstract: This work introduces two techniques to ameliorate high-resolution TDC performance: a precise TDC calibration algorithm and a background mismatch correction algorithm. To demonstrate the proposed techniques we have realized a 3GHz fractional synthesizer based on an 8ps resolution TDC in standard 65nm CMOS. The prototype uses a 25MHz reference and consumes 9.5mW excluding test buffers. The bandwidth is programmable from 100kHz to 2MHz, in-band phase noise is -100dBc/Hz and the worst-case in-band spur, after correction, is -45dBc. This is the first prototype with low phase noise, spur suppression and wide-bandwidth known to the authors. Moreover, it is competitive with fractional-N analog PLLs.

A parallelized way to provide data encryption and integrity checking on a processor-memory bus

Abstract: This paper describes a novel engine, called PE-ICE (parallelized encryption and integrity checking engine), enabling to guarantee confidentiality and integrity of data exchanged between a SoC (system on chip) and its external memory. The PE-ICE approach is based on an existing block-encryption algorithm to which the integrity checking capability is added. Simulation results show that the performance overhead of PE-ICE remains low (below 4%) compared to block-encryption-only systems (which provide data confidentiality only).

Near infrared/color image sensor

Abstract: A near infrared/color photodetector made in a monolithic form in a lightly-doped substrate of a first conductivity type covering a holder and comprising a face on the side opposed to the holder. The photodetector includes at least first and second photodiodes for the storage of electric charges photogenerated in the substrate, the second photodiode being adjacent to said face; and a first region extending at least between the second photodiode and the holder, preventing the passage of said charges between a first substrate portion being located between said region and the holder and a second substrate portion extending between said face and the first region, the first photodiode being adapted to store at least charges photogenerated in the first substrate portion and the second photodiode being adapted to store charges photogenerated in the second substrate portion.

Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations

Abstract: Transmission lines are becoming of common use at mm-wave to implement on-chip functions as impedance matching, filtering and interconnects. Lack of an accurate and fast simulation method is nonetheless evident for transmission lines in scaled CMOS where metal dummies inserted for IC planarization make their physical structure extremely complicate. Although lines are not uniform due to displacement of small dummies, they are still periodic. In this paper, we describe an analytical procedure, leveraging lines periodicity and based on Floquet's theorem, in order to derive electromagnetic parameters from simulations. Conventional, slow-wave and shielded CPWs have been realized in a 65 nm CMOS technology. Thanks to the developed method, an optimum line design has been made possible. The lossy CMOS substrate, responsible for a significant performance degradation, can be effectively shielded and achieved performances are comparable with other technologies considered better suited to implement low-loss, high frequency passive components. Shielded CPW lines show attenuation as low as 0.65 dB/mm at 60 GHz, a record in scaled CMOS.