STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Method for the implementation of modular multiplication according to the Montgomery method

Abstract: A method for the implementation of modular multiplication according to the Montgomery method, wherein a multiplicand A and a multiplier B are encoded respectively on a and b words of k bits, the most significant words of A and B being non-zero, a modulo N is encoded on m words of k bits, the modulo having (m-m') most significant words with k zero bits, with 0

Ultrasensitive Label- and PCR-Free Genome Detection Based on Cooperative Hybridization of Silicon Nanowires Optical Biosensors

Abstract: The realization of an innovative label- and PCR-free silicon nanowires (NWs) optical biosensor for direct genome detection is demonstrated. The system is based on the cooperative hybridization to selectively capture DNA and on the optical emission of quantum confined carriers in Si NWs whose quenching is used as detection mechanism. The Si NWs platform was tested with Hepatitis B virus (HBV) complete genome and it was able to reach a Limit of Detection (LoD) of 2 copies/reaction for the synthetic genome and 20 copies/reaction for the genome extracted from human blood. These results are even better than those obtained with the gold standard real-time PCR method in the genome analysis. The Si NWs sensor showed high sensitivity and specificity, easy detection method, and low manufacturing cost fully compatible with standard silicon process technology. All these points are key factors for the future development of a new class of genetic point-of-care devices that are reliable, fast, low cost, and easy to use ...

25.5 A 320GHz phase-locked transmitter with 3.3mW radiated power and 22.5dBm EIRP for heterodyne THz imaging systems

Abstract: Non-ionizing terahertz imaging using solid-state integrated electronics has been gaining increasing attention over the past few years. However, there are currently several factors that deter the implementations of fully-integrated imaging systems. Due to the lack of low-noise amplification above f max , the sensitivity of THz pixels on silicon cannot match that of its mm-Wave or light-wave counterparts. This, combined with the focal-plane array configuration adopted by previous sensors, requires exceedingly large power for the illumination sources. Previous works on silicon have demonstrated 1mW radiation [1,3]; but higher power, as well as energy efficiency, are needed for a practical imaging system. In addition, heterodyne imaging scheme was demonstrated to be very effective in enhancing detection sensitivity [4]. Due to the preservation of phase information, it also enables digital beam forming with a small number of receiver units. This however requires phase locking between the THz source and receiver LO with a small frequency offset (IF<1GHz). In [5], a 300GHz PLL is reported with probed output. In this paper, a 320GHz transmitter using SiGe HBTs is presented (Fig. 25.5.1). Combining 16 coherent radiators, this work achieves 3.3mW radiated power with 0.54% DC-RF efficiency, which are the highest among state-of-the-art silicon THz radiators shown in the comparison table in Fig. 25.5.6. Meanwhile, the output beam is phase-locked by a fully-integrated PLL, which enables high-performance heterodyne imaging systems.

Process for fabricating a substrate of the silicon-on-insulator or silicon-on-nothing type and resulting device

Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

A 56-mW 23-mm/sup 2/ single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm/sup 2/ radio

Abstract: A 56-mW 23-mm/sup 2/ GPS receiver with CPU-DSP-64 kRAM-256 kROM and a 27.2-mW 4.1-mm/sup 2/ radio has been integrated in a 180-nm CMOS process. The SoC GPS receiver, connected to an active antenna, provides latitude, longitude, height with 3-m rms precision with no need of external host processor in a [-40, 105]/spl deg/C temperature range. The radio draws 17 mA from a 1.6-1.8-V voltage supply, takes 11 pins of a VFQFPN68 package, and needs just a few passives for input match and a crystal for the reference oscillator. Measured radio performances are NF=4.8 dB, Gp=92 dB, image rejection > 30 dB, -112 dBc/Hz phase noise @ 1 MHz offset from carrier. Though GPS radio linearity and ruggedness have been made compatible with the co-existence of a microprocessor, radio silicon area and power consumption is comparable to state-of-the-art stand-alone GPS radio. The one reported here is the first ever single-chip GPS receiver requiring no external host to achieve satellite tracking and position fix with a total die area of 23 mm/sup 2/ and 56-mW power consumption.