STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

A 56-mW 23-mm/sup 2/ single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm/sup 2/ radio

Abstract: A 56-mW 23-mm/sup 2/ GPS receiver with CPU-DSP-64 kRAM-256 kROM and a 27.2-mW 4.1-mm/sup 2/ radio has been integrated in a 180-nm CMOS process. The SoC GPS receiver, connected to an active antenna, provides latitude, longitude, height with 3-m rms precision with no need of external host processor in a [-40, 105]/spl deg/C temperature range. The radio draws 17 mA from a 1.6-1.8-V voltage supply, takes 11 pins of a VFQFPN68 package, and needs just a few passives for input match and a crystal for the reference oscillator. Measured radio performances are NF=4.8 dB, Gp=92 dB, image rejection > 30 dB, -112 dBc/Hz phase noise @ 1 MHz offset from carrier. Though GPS radio linearity and ruggedness have been made compatible with the co-existence of a microprocessor, radio silicon area and power consumption is comparable to state-of-the-art stand-alone GPS radio. The one reported here is the first ever single-chip GPS receiver requiring no external host to achieve satellite tracking and position fix with a total die area of 23 mm/sup 2/ and 56-mW power consumption.

Programmable bandwidth voltage regulator

Abstract: A method for reducing the transient response time of a voltage regulator when the load attached to it is entering or exiting a lower power consumption level by changing the bandwidth of the voltage regulator without compromising its stability, and a bandwidth regulator for implementing such a method are disclosed, wherein the bandwidth of the voltage regulator is changed based on a signal sent by a control device when it senses that the component is about to change power consumption levels.

2.10 A 60GHz 28nm UTBB FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18.2dBm P 1dB and 74mW P DC

Abstract: The widespread deployment of high-data-rate wireless connectivity was enabled by the adoption of the WiGig (802.11ad) standard, consequently placing a challenge on integrated Power Amplifiers (PAs). To comply with system requirements, the PA must cover bands from 57 to 66GHz and deliver up to 10dBm RF modulated power, while OFDM modulations up to 16 or 64QAM are supported, implying a large Peak-to-Average Power Ratio (PAPR).

Single feature size MOS technology power device

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

Memory device having error detection and correction function, and methods for reading, writing and erasing the memory device

Abstract: The present invention relates to a memory device and specifically the multilevel type with error check and correction function and having a data input (DI), a data output (DO) and an address input (AI) and being of the type comprising first memory means (DM) designed to be accessed by means of address for containing user data, second memory means (EM) for containing error data concerning said user data, a control logic (CL) designed to receive in the writing phase from said address input (AI) and said data input (DI) a writing address and user data respectively and to generate error data and to write said data in said first means (DM) and second means (EM) respectively and designed to receive in the reading phase from said address input (AI) a reading address and extract corresponding user data and error data and combine them to correct any errors and supply them to said data output (DO) and characterised in that said second means (EM) are the type designed to be accessed by means of content and said content for access corresponding to addresses of said first means (DM).