STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking

Abstract: Wide voltage range operation for DSPs brings more versatility to achieve high energy efficiency in mobile applications. This paper describes a 32 bits DSP fabricated in 28 nm Ultra Thin Body and Box FDSOI technology. Body Biasing Voltage (VBB) scaling from 0 V up to ±2 V decreases the core VDDMIN to 397 mV and increases clock frequency by +400%@500 mV and +114%@1.3 V. The DSP frequency measurements show 2.6 GHz@1.3 V(VDD)@2 V(VBB) and 460 MHz@397 mV(VDD)@2 V(VBB). The lowest peak energy efficiency is measured at 62 pJ/op at 0.53 V. In addition to technological gains, maximum frequency tracking design techniques are proposed for wide voltage range operation. On silicon, at 0.6 V, those techniques allow high energy gain of 40.6% w.r.t. a worst case corner approach.

Switching and programming dynamics in phase-change memory cells

Abstract: Emerging phase-change memory (PCM) technology for non-volatile applications presents many potential advantages in terms of scalability, endurance and program/read speed. While several integration issues have still to be solved before achieving volume-production stage, the fundamental physics of chalcogenide switching and phase-change behaviour has still to be comprehensively understood. This paper provides an in-depth analysis of the switching and programming transient in PCM cells. It is shown that the cell parasitic capacitance can lead to a marked current overshoot in the programming transient. As evidenced by experiments, this overshoot is able to melt and quench the active material as in a reset operation. The parasitic reset results in a series distribution of crystalline and amorphous phases after program. The analysis of array cell capacitance instead indicates that no parasitic reset is to be expected, allowing for a localized crystallization during program, as previously obtained by numerical simulations.

Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip

Abstract: Clock distribution is an important issue when designing multi processor systems-on-chip on deep sub-micron technology nodes and non-synchronous approaches are becoming popular in this field. This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads; moreover it can be easily integrated in a conventional digital design flow since it is implemented by means of standard cells only. Results are presented referring to the link integrated within a multi processor tiled architecture based on a network-on-chip communication backbone on a CMOS 65 nm technology.

Reduced pressure chemical vapour deposition of SiGe virtual substrates for high mobility devices

Abstract: We have studied the strain state, film and surface morphology of SiGe virtual substrates grown by reduced pressure chemical vapour deposition (RP-CVD). The macroscopic strain relaxation and the Ge composition of those virtual substrates have been estimated in high resolution x-ray diffraction, using Omega-2Theta scans around the (004) and (224) orders. Typically, linearly graded Si0.7Ge0.3 virtual substrates 5 ?m thick are 96% relaxed. From transmission electron microscopy, we confirm that the misfit dislocations generated to relax the lattice mismatch between Si and SiGe are mostly confined inside the graded layer. The threading dislocations density obtained for Ge concentrations of 20% and 27% is indeed typically of the order of (7.5 ? 2.5) ?105 cm?2. The surface roughness of the relaxed SiGe virtual substrates increases significantly as the Ge concentration approaches 30%. We find for the technologically important Ge concentration of 30% a surface root mean square roughness of 5 nm, with an undulation wavelength for the cross-hatch of the order of 1 ?m. We have also studied the electronic quality of our RP-CVD grown SiGe virtual substrates. We have grown a MODFET-like heterostructure for this purpose, with a buried tensile-strained Si channel 8 nm thick embedded inside SiGe 31%. We have obtained a well-behaved two-dimensional electron gas in the Si channel, with electron sheet densities and mobilities at 1.45 K of 5.7 ? 1011 cm?2 and 180?000 cm2 V?1 s?1, respectively.

Picture processing system

Abstract: A system that processes compressed data arriving in packets corresponding to picture blocks, the packets being separated by headers containing decoding parameters of the packets. A memory bus is controlled by a memory controller to exchange data between the processing elements and a picture memory. A pipeline circuit contains a plurality of processing elements. A parameter bus provides packets to be processed to the pipeline circuit, as well as the decoding parameters to elements of the system. The parameter bus is controlled by a variable length decoder that receives the compressed data from the memory bus and that extracts the packets and the decoding parameters therefrom.