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Institution

STMicroelectronics

CompanyGeneva, Switzerland
About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.


Papers
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Patent
25 Nov 1997
TL;DR: In this paper, a method of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed, where an opening is formed partially through an insulating layer overlying a conductive region.
Abstract: A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening. According to a further alternate embodiment, an etch stop layer is formed between the insulating layer and conductive region and an opening is formed in the insulating layer exposing the etch stop layer. A sidewall spacer film is formed over the insulating layer and the etch stop layer, both layers having a similar etch rate for a given etchant. The etch stop and spacer layers are etched in the opening to expose the underlying conductive layer thereby forming a contiguous sidewall spacer and etch stop layer on the sides of and under the insulating layer, thereby decreasing the contact dimension of the opening.

51 citations

Journal ArticleDOI
TL;DR: In this article, the results of a new epitaxial process using an industrial 6x2” wafer reactor with the introduction of HCl during the growth have been reported.
Abstract: The results of a new epitaxial process using an industrial 6x2” wafer reactor with the introduction of HCl during the growth have been reported. A complete reduction of silicon nucleation in the gas phase has been observed even for high silicon dilution parameters (Si/H2>0.05) and an increase of the growth rate until about 20 µm/h has been measured. No difference has been observed in terms of defects, doping uniformity (average maximum variation 8%) and thickness uniformity (average maximum variation 1.2 %) with respect to the standard process without HCl.

51 citations

Patent
17 Jun 1994
TL;DR: In this paper, a voltage multiplier for relatively high output current has its design output voltage stabilized and rendered independent of process spread, temperature, supply voltage and output current level, by a stabilization loop driving the switch that cyclically connects to ground a charge transfer capacitance of the functional voltage multiplier circuit.
Abstract: A voltage multiplier for relatively high output current has its design output voltage stabilized and rendered independent of process spread, temperature, supply voltage and output current level, by a stabilization loop driving the switch that cyclically connects to ground a charge transfer capacitance of the functional voltage multiplier circuit. The feedback loop comprises an integrating stage, stabilized by creating a low-frequency zero in the transfer function for compensating one of two low-frequency poles of the transfer function of the whole circuit.

51 citations

Proceedings ArticleDOI
26 Apr 2004
TL;DR: An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Comp compressor, using 0.13um technology.
Abstract: An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13um technology.

51 citations

Patent
03 May 2006
TL;DR: In this article, a method for generating a succession of pseudo-random numbers includes choosing at least one chaotic map, and choosing a seed for chaotic map and a number of iterations for the chaotic map.
Abstract: A method for generating a succession of pseudo-random numbers includes choosing at least one chaotic map, and choosing a seed for the chaotic map and a number of iterations for the chaotic map. The succession of pseudo-random numbers are generated by executing iteratively generating a pseudo-random number as a function of a final state reached by the chaotic map iterated for the current number of iterations starting from the current seed, and generating a new seed for the chaotic map or a new number of iterations as a function of the final state.

51 citations


Authors

Showing all 17185 results

NameH-indexPapersCitations
Bharat Bhushan116127662506
Albert Polman9744542985
G. Pessina8482830807
Andrea Santangelo8388629019
Paolo Mattavelli7448219926
Daniele Ielmini6836716443
Jean-François Carpentier6245914271
Robert Henderson5844013189
Bruce B. Doris5660412366
Renato Longhi551778644
Aldo Romani5442511513
Paul Muralt5434412694
Enrico Zanoni5370513926
Gaudenzio Meneghesso5170312567
Franco Zappa502749211
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
202225
2021560
2020798
2019952
2018948
2017781