STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact

Abstract: Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross-section and dye penetration test.

A 32x32 50ps Resolution 10 bit Time to Digital Converter Array in 130nm CMOS for time Correlated Imaging

Abstract: (SUMMARY e report the design and characterisation of a 32x32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50μm pitch TDC array exhibits a minimum time resolution of 50ps, with accuracy of ±0.5 LSB DNL and 2.4 LSB INL. Process, voltage and temperature compensation (PVT) is achieved by locking the array to a stable external clock. The resulting time correlated pixel array is a viable candidate for single photon counting (TCSPC) applications such as fluorescent lifetime imaging microscopy (FLIM), nuclear or 3D imaging and permits scaling to larger array formats.

Compound camera sensor and related method of processing digital images

Abstract: In one embodiment, a light sensor includes four cell arrays, one for each color of the Bayer pattern, and four lenses each focusing the light coming from the scene to be captured on a respective cell array. The lenses are oriented such that at least a second green image, commonly provided by the fourth cell array, is both horizontally and vertically shifted (spaced) apart by half a pixel pitch from a first (reference) green image. In a second embodiment, the four lenses are oriented such that the red and blue images are respectively shifted (spaced) apart by half a pixel pitch from the first or reference green image, one horizontally and the other vertically, and the second green image is shifted (spaced) apart by half a pixel pitch from the reference green image both horizontally and vertically.

Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature

Abstract: Channel Hot-Carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias V BS . A three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the V GS , V DS (V BS ) conditions as a single I DS lifetime dependence is observed with V GD > 0. This gives a new age(t) function useful for accurate DC to AC transfers. Positive temperature activation is explained by the rise of ionization rate with electron-electron scattering (medium I DS ) and multi vibrational excitation (higher I DS ) which increase the H desorption by thermal emission. The use of forward VBS has shown no gain under CHC for both device types. The main limitation occurs under reverse V BS = −V DD in IO where the smaller temperature activation partially compensates the larger damage. In that case a security margin can be established giving a limit of V BS = −V DD /2 for design reliability.

An 8Mb demonstrator for high-density 1.8V Phase-Change Memories

Abstract: An 8Mb Non-Volatile Memory Demonstrator incorporating a novel 0.32 /spl mu/m/sup 2/ Phase-Change Memory (PCM) cell using a Bipolar Junction Transistor (BJT) as selector and integrated into a 3V 0.18 /spl mu/m CMOS technology is presented. Realistically large 4Mb tiles with a voltage regulation scheme that allows fast bitline precharge and sense are proposed. An innovative approach that minimizes the array leakage has been used to verify the feasibility of high-density PCM memories with improved Read/Write performance compared to Flash. Finally, cells distributions and first endurance measurements demonstrate the chip functionality and a good working window.