STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Understanding and addressing the impact of wiring congestion during technology mapping

Abstract: Traditionally, interconnect effects are taken into account duringlogic synthesis via wireload models, but their ineffectiveness forDSM technologies has been demonstrated and various physicalsynthesis approaches have been spawned to address the problem. Ofparticular interest is that logic block size is no longer dictatedexclusively by total cell area, yet synthesis optimizationobjectives are aimed specifically at minimizing the number and sizeof cells. Methodologies that incorporate congestion within thelogic synthesis objective function have been proposed in[9][10][11] and [15]; however, as we will demonstrate, predictingthe true congestion prior to layout is not possible, and theefficacy of any approach can only be evaluated after routing iscompleted within the fixed die size. In this paper we propose apractical, complete methodology which first performscongestion-aware technology mapping using a global weighting factorfor the cost function [15], and then applies incremental localizedunmapping and remapping on congested areas. This complete approachaddresses the problem that one global factor is not ideally suitedfor all regions of the designs. Most importantly, through theapplication of this methodology to industrial examples we will showthat any attempt at a purely top-down single-pass congestion-awaretechnology mapping is merely wishful thinking.

Radiation induced leakage current and stress induced leakage current in ultra-thin gate oxides

Abstract: Low-field leakage current has been measured in thin oxides after exposure to ionising radiation. This Radiation Induced Leakage Current (RILC) can be described as an inelastic tunnelling process mediated by neutral traps in the oxide, with an energy loss of about 1 eV. The neutral trap distribution is influenced by the oxide field applied during irradiation, thus indicating that the precursors of the neutral defects are charged, likely to be defects associated with trapped holes. The maximum leakage current is found under zero-field condition during irradiation, and it rapidly decreases as the field is enhanced, due to a displacement of the defect distribution across the oxide towards the cathodic interface. The RILC kinetics are linear with the cumulative dose, in contrast with the power law found on electrically stressed devices.

On-chip error correcting techniques for new-generation flash memories

Abstract: In new-generation flash memories, issues such as disturbs and data retention become more and more critical as a consequence of reduced cell size and decreased oxide thickness. Furthermore, the progressive increase in the cell count within a single die tends to decrease device reliability. In particular, reliability issues turn out to be more critical in multilevel (ML) flash memories, due to the reduced spacing between adjacent programmed levels. It is therefore deemed that the use of on-chip error correction codes (ECCs) will gain widespread acceptance in large-capacity flash memories. ECCs for flash memories must have very fast and compact encoding/decoding circuitry so as to have a minimum impact on memory access time. The area penalty due to check cells must also be minimized. Moreover, specific codes must be developed for ML storage. This paper presents error control coding techniques and schemes for new-generation flash memories, focusing on ML devices. The basic concepts of error control coding are reviewed, and the on-chip ECC design procedure is analyzed. Dedicated codes such as polyvalent ECCs, able to correct data stored in ML memories working at a variable number of bits per cell, and bit-layer organized ECCs are described.

Comparison of the Device Lifetime in Wireless Networks for the Internet of Things

Abstract: This paper presents a comparison of the expected lifetime for Internet of Things (IoT) devices operating in several wireless networks: the IEEE 802.15.4/e, Bluetooth low energy (BLE), the IEEE 802.11 power saving mode, the IEEE 802.11ah, and in new emerging long-range technologies, such as LoRa and SIGFOX. To compare all technologies on an equal basis, we have developed an analyzer that computes the energy consumption for a given protocol based on the power required in a given state (Sleep, Idle, Tx, and Rx) and the duration of each state. We consider the case of an energy constrained node that uploads data to a sink, analyzing the physical (PHY) layer under medium access control (MAC) constraints, and assuming IPv6 traffic whenever possible. This paper considers the energy spent in retransmissions due to corrupted frames and collisions as well as the impact of imperfect clocks. The comparison shows that the BLE offers the best lifetime for all traffic intensities in its capacity range. LoRa achieves long lifetimes behind 802.15.4 and BLE for ultra low traffic intensity; SIGFOX only matches LoRa for very small data sizes. Moreover, considering the energy consumption due to retransmissions of lost data packets only decreases the lifetimes without changing their relative ranking. We believe that these comparisons will give all users of IoT technologies indications about the technology that best fits their needs from the energy consumption point of view. Our analyzer will also help IoT network designers to select the right MAC parameters to optimize the energy consumption for a given application.