STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit

Abstract: As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its nonvolatility and high write/read speed allow to power down completely the logic blocks in “idle” states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM technology are presented in this article. By using STMicroelectronics CMOS 90nm technology and a STT-MTJ spice model, some chip characteristic results as the programming latency and power have been calculated and simulated to demonstrate the expected performance of STT-MRAM based FPGA logic circuits.

Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 /spl mu/m CMOS process

Abstract: ESD protection for RF applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfil these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 /spl mu/m CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme. The optimization of the diodes is then a key point which is detailed. A trade-off must be found between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as STI bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice.

Improved direct back EMF detection for sensorless brushless DC (BLDC) motor drives

Abstract: Improved back EMF detection circuits for low voltage/low speed and high voltage sensorless BLDC motor drives are presented in this paper. The improvements are based on the direct back EMF sensing method from our previous research work described in reference, which describes a technique for directly extracting phase back EMF information without the need to sense or re-construct the motor neutral. The reference method is not sensitive to switching noise and requires no filtering, achieving much better performance than traditional back EMF sensing scheme. A complementary PWM (synchronous rectification) is proposed to reduce the power dissipation in power devices for low voltage applications. In order to further extend the sensorless BLDC system to lower speed, a pre-conditioning circuit is proposed to amplify the back EMFs at very low speed. As a result, the brushless DC motor can run at lower speed with the improved back EMF sensing scheme. On the other hand, another improved detection circuit is presented for high voltage applications to overcome the delaying problem caused by large sensing resistors. The detailed circuit models are analyzed and experimental results verify the analysis.

Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture

Abstract: Lateral field penetration in the buried oxide (BOX) and underlying substrate of fully depleted SOI MOSFETs is responsible for a dramatic increase of short-channel effects. An original compact model of the latter phenomena is proposed and used to explore optimized architectures of sub-100 nm transistors. Various architectures including the ground-plane MOSFET, are compared using a quasi-2D analysis in order to evaluate the contribution of the BOX to short-channel effects.

Characteristics of the Electrical Percolation in Carbon Nanotubes/Polymer Nanocomposites

Abstract: We study the onset of electrical percolation in multiwalled carbon nanotubes (MWNTs)/epoxy nanocomposites. Experiments show a threshold value of 3.2 wt % of MWNTs for percolation to occur. Simulations based on two varied approaches are carried out to evaluate the conductivity characteristics resulting from increasing MWNT content. Simple Monte Carlo simulations in which MWNTs are modeled as either 1D sticks or 2D narrow rectangles dispersed in a 2D simulation volume are shown to yield a percolation threshold in close agreement with experiments. We find that a higher degree of anisotropy in the orientation of nanotubes or of the waviness leads to an increase in the percolation threshold. A more insightful approach encompassing the quantum tunneling effect is also undertaken using the tight-binding simulations. Consideration of the tunneling effect is found to be particularly important when the nanotube aspect ratio is small, the case in which simpler Monte Carlo simulations overestimate the percolation thr...