STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Electrical Behavior of Phase-Change Memory Cells Based on GeTe

Abstract: In this letter, we present a study on the electrical behavior of phase-change memories (PCMs) based on a GeTe active material. GeTe PCMs show, first, extremely rapid SET operation (yielding a gain of more than one decade in energy per bit with respect to standard GST PCMs), second, robust cycling, up to 1 × 105, with 30-ns SET and RESET stress time, and third, a better retention behavior at high temperature with respect to GST PCMs. These results, obtained on single cells, suggest GeTe as a promising alternative material to standard GST to improve PCM performance and reliability.

What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

Abstract: Parameters limiting the improvement of high frequency characteristics for deep submicron MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that for MOSFETs with optimized source, drain and gate access, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high frequency performance of ultra deep submicron MOSFETs.

Board level drop test and simulation of TFBGA packages for telecommunication applications

Abstract: Reliabilit!- perfonnance of IC packages during drop impact is critical, especially for handheld electronic products. Currently. thcrc is no detailed test standard in the industry to advise on the procedures for board level dmp test. nor there is any model Ilia1 providcs good correlation with experimental ineasiircinents of acceleration and impact life. In this paper; detailed drop tests and simulations are pcrfonned on TFBGA (Thin-profile Fine-pitch BGA) and VFBGA (Vey-thinprofile Fine-pitch BGA) packages at board level using testing procediires developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and iueclwnical shock during impact. The critical solder ball is obsewed to occur at the outennost comer solder .joint_ and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically. to understand the effects of drop heightl drop oricntation, number of PCB mounting screws to fixture. position of component on board: PCB bending: solder material, and etc. Drop height, fclt thickness, and contact conditions are used to fine-tune the shape aud level of shock pulse required. Board level drop test can be better controlled. compared with system or product level test such as impact of mobile phone. which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At tlie same time, dynamic simulation is perfonncd to compare with esperiniental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estiinatc the number of drops to failure for a package. For the correlation cases studied. the nminmm nonual peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within M drops, for a typical test of 50 drops. With this new model, a failure-free state can be detennined, and drop test performance of new package design can be quantified. and fuliher enhanced through modeling. This quantitative approach is different from traditional qualitative modeling. as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test ,and thennal cycling test. Different design guidelines should be considered, depcnding on application and area of concern

Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility

Abstract: In this paper, an experimental investigation on high-temperature carrier mobility in bulk silicon is carried out with the aim of improving our qualitative and quantitative understanding of carrier transport under ESD events. Circular van der Pauw patterns, suitable for resistivity and Hall measurements, were designed and manufactured using both the n and p layers made available by the BCD-3 smart-power technology. The previous measurements were carried out using a special measurement setup that allows operating temperatures in excess of 400/spl deg/C to be reached within the polar expansions of a commercial magnet. A novel extraction methodology that allows for the determination of the Hall factor and drift mobility against impurity concentration and lattice temperature has been developed. Also, a compact mobility model suitable for implementation in device simulators is worked out and implemented in the DESSIS/spl copy/ code. Comparisons with the mobility models by G. Masetti et al. (1983) and D.B.M. Klaassen (1992) are shown in the temperature range between 25 and 400/spl deg/C.

Unbounded page-based transactional memory

Abstract: Exploiting thread level parallelism is paramount in the multicore era Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model Virtualized transactions (unbounded in space and time) are desirable, as they can increase the scope of transactions' use, and thereby further simplify a programmer's job However, hardware support is essential to support efficient execution of unbounded transactions In this paper, we introduce Page-based Transactional Memory to support unbounded transactions We combine transaction bookkeeping with the virtual memory system to support fast transaction conflict detection, commit, abort, and to maintain transactions' speculative data