STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

A Low-Noise Design Technique for High-Speed CMOS Optical Receivers

Abstract: A careful comparison between alternative topologies to realize low-noise wideband TIAs is carried out in this work. In order to break the tradeoff between noise and bandwidth, the proposed front-end uses two stages, i.e. a low-noise narrowband transimpedance interface followed by an equalizer aimed at restoring the required bandwidth. The technique is especially effective for white noise components. The core first-stage amplifier exploits current reuse for minimum power consumption and is optimized for colored noise reduction. A net 4 $\times$ noise power reduction is achieved if compared with a design approach based on a traditional shunt-feedback TIA with the same bandwidth. A complete receiver, interfacing a commercial photodiode, and including the proposed two-stage front-end (TSFE), a limiting amplifier and a wideband output buffer has been realized in 65 nm CMOS. Optical communications tailored to 100GBASE-LR4 standard, which is specified for mid-to-long range transmissions at a channel rate of 25 Gb/s, are targeted. Realized prototypes show a sensitivity of $-$ 11.9 dBm at a BER of $10^{-12}$ with a PRBS31 input pattern and a transimpedance gain of 83 $\hbox{dB}\Omega$ , while tolerating an overall input capacitance of 160 fF. To the best of the authors' knowledge, this is the best sensitivity performance achieved by 25-Gb/s optical receivers in CMOS, comparable to state-of-the-art BiCMOS realizations.

A Multi-Level-Cell Bipolar-Selected Phase-Change Memory

Abstract: Phase-change memory (PCM) is becoming widely recognized as the most likely candidate to unify the many memory technologies that exist today (Lee, et al., 2007). The combination of non-volatile attributes of flash, RAM-like bit-alterability, and fast reads and writes position PCM to enable changes in the memory subsystems of cellular phones, PCs and countless embedded and consumer electronics applications. This design's multi-level cell (MLC) capabilities combined with long- term scalability reduce PCM costs as only realized before by hard disk drives. MLC technology is challenged with fitting more cell states (4 in the case of 2 bit per cell), along with distribution spreads due to process, design, and environmental variations, within a limited window. We describe a 256Mb MLC test-chip in a 90nm micro-trench (mutrench) PCM technology, and MLC endurance results from an 8Mb 0.18mum PCM test-chip with the same trench cell structure. A program algorithm achieving tightly placed inner states and experimental results illustrating distinct current distributions are presented to demonstrate MLC capability.

A Reconfigurable 3-D-Stacked SPAD Imager With In-Pixel Histogramming for Flash LIDAR or High-Speed Time-of-Flight Imaging

Abstract: A 256 $\times $ 256 single-photon avalanche diode (SPAD) sensor integrated into a 3-D-stacked 90-nm 1P4M/40-nm 1P8M process is reported for flash light detection and ranging (LIDAR) or high-speed direct time-of-flight (ToF) 3-D imaging. The sensor bottom tier is composed of a 64 $\times $ 64 matrix of 36.72- $\mu \text{m}$ pitch modular photon processing units which operate from shared $4\,\,\times $ 4 SPADs at 9.18- $\mu \text{m}$ pitch and 51% fill-factor. A 16 $\times $ 14 bit counter array integrates photon counts or events to compress data to 31.4 Mb/s at 30-frame/s readout over 8 I/O operating at 100 MHz. The pixel-parallel multi-event time-to-digital converter (TDC) approach employs a programmable internal or external clock for 0.56–560-ns time bin resolution. In conjunction with a per-pixel correlator, the power is reduced to less than 100 mW in practical daylight ranging scenarios. Examples of ranging and high-speed 3-D ToF applications are given.

A thorough investigation of progressive breakdown in ultra-thin oxides. Physical understanding and application for industrial reliability assessment

Abstract: This paper provides a close investigation of the gate oxide failure for thickness below 24/spl Aring/. At first, the failure detection is discussed showing that its manifestation is not catastrophic any more. Then, the wear-out beginning at the failure occurrence is studied. It highlights the path conduction aging whose progressiveness is found to be mainly gate voltage driven. At last, progressiveness dynamics is investigated and a methodology is developed to rigorously relax the reliability criterion following applications.