STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Maximization of layout printability/manufacturability by extreme layout regularity

Abstract: In the past, complying with design rules was sufficient to ensure acceptable yields for a design. However, for sub-100-nm designs, this approach tends to create patterns that cannot be reliably printed for a given optical setup, thus leading to hot spots and systematic yield failures. Recent challenges faced by both the design and process communities call for a paradigm shift whereby circuits are constructed from a small set of lithography-friendly patterns that have previously been extensively characterized and ensured to print reliably. We describe the use of a regular design fabric for defining the underlying layout geometries of the circuit. While the direct application of this methodology to the current application-specific integrated circuit (ASIC) design flow would result in unnecessary area and performance penalties, we overcome these penalties via a unique design flow that ensures shape-level regularity by reducing the number of required logic functions as much as possible as part of the top-down design flow. We show that with a small set of Boolean functions and careful selection of lithography-friendly patterns, we not only mitigate but essentially eliminate such penalties. Additionally, we discuss the benefits of using extremely regular designs constructed from a limited set of lithography-friendly patterns not only to improve manufacturability but also to relax the pessimistic constraints defined by design rules. Specifically, we introduce the basis to exploit the regularity in the layout patterns by using "pushed-rules" for logic design, as is commonly done for static random access memory (SRAM). This in turn facilitates a common optical proximity correction (OPC) methodology for logic and SRAM. Moreover, by taking advantage of this newfound manufacturability and predictability of regular circuits, we show that the performance of logic built on regular fabrics can surpass that of seemingly more arbitrarily constructed logic.

An Integrated 13.56-MHz RFID Tag in a Printed Organic Complementary TFT Technology on Flexible Substrate

Abstract: This paper presents the first printed organic 13-MHz RFID on flexible substrate The proposed solution includes a planar near field antenna bonded to an RFID tag, which is printed on flexible foil using an organic complementary TFT technology Thanks to an active envelope detector, ASK modulation with modulation depth as low as 20% can be adopted to increase the available input power for the rectifier The RFID functionality is demonstrated at the internally generated supply voltage of 24 V, for a reading range of 2–5 cm and a bit-rate up to 50 bit/s With more than 250 transistors on the same foil, this work represents the most complex circuit ever published in a printed organic complementary TFT technology

A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput

Abstract: A 90 nm 4 Mb embedded phase-change memory (PCM) is presented, demonstrating the feasibility of PCM integration with 3 masks overhead in a 6-ML standard CMOS process. Using a low-voltage NMOS transistor as a cell selector leads to a 0.29 ?m2 cell size. A 1.2 V low-voltage read operation achieves a 12 ns access time. The 3 mm2 macro features a random write throughput of 1 MB/s and a mode to increase write throughput to 4 MB/s.

A 1kpixel CMOS camera chip for 25fps real-time terahertz imaging applications

Abstract: Future imaging applications in the submillimeter-Wave range (300GHz to 3THz) require RF systems that can achieve high sensitivity and portability at low power consumption levels. In particular, CMOS process technologies are attractive due to their low price tag for industrial, surveillance, scientific, and medical applications. Recently, CMOS-based detectors have shown good sensitivity up to 1THz with NEPs on the order of 66pW/√(Hz) at 1THz [1]. However, CMOS terahertz imagers developed thus far have only operated single detectors based on lock-in measurement techniques to acquire raster-scanned images with frame rates on the order of minutes [2]. To address these impediments, we present a low-power 1kpixel terahertz camera chip fully compliant with an industrial 65nm f t /f max =160GHz/200GHz CMOS process technology. The active-pixel circuit topology is designed to accommodate the optics for wide bandwidth (0.6 to 1THz) in stand-off detection with a 40dBi Si-lens. It includes row/col select and integrate-and-dump circuitry capable of capturing terahertz images with video frame rates up to 25fps at a power consumption of 2.5μW/pixel.

Process for forming front-back through contacts in micro-integrated electronic devices

Abstract: The process comprises the steps of: forming a through hole from the back of a semiconductor material body; forming a hole insulating layer of electrically isolating material laterally covering the walls of the through hole; forming a through contact region of conductive material laterally covering the hole insulating layer inside the hole and having at least one portion extending on top of the lower surface of the body; forming a protective layer covering the through contact region; and forming a connection structure extending on top of the upper surface of the body between and in electrical contact with the through contact region and the electronic component.