STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Through-package-via formation and metallization of glass interposers

Abstract: Interposer technology has evolved from ceramic to organic materials and most recently to silicon. Organic substrates exhibit poor dimensional stability, thus requiring large capture pads which make them unsuitable for very high I/Os with fine pitch interconnections. Therefore, there has been a trend to develop silicon interposers. Silicon interposers however, suffer in two ways; 1) they are expensive to process due to the need for electrical insulation around via walls, and 2) they are limited in size by the silicon wafer from which they originate. In this paper, glass is proposed as a superior alternative interposer technology to address the limitations of both silicon and organic interposers. The inherent electrical properties of glass, together with large area panel size availability, make it superior compared to organic and silicon-based interposers. Glass however, is not without its challenges. It suffers in two ways: 1) formation of vias at low cost, and 2) its lower thermal conductivity compared to silicon. This research explores glass as an interposer material, and addresses the above key challenges in through package via (TPV) formation and subsequent low cost and large area metallization to achieve very high I/Os at fine pitch.

Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction device for hybrid Magnetic-CMOS design

Abstract: The development of hybrid Magnetic-CMOS circuits such as MRAM (Magnetic RAM) and Magnetic logic circuit requires efficient simulation models for the magnetic devices. A macro-model of Magnetic Tunnel Junction (MTJ) is presented in this paper. This device is the most commonly used magnetic components in CMOS circuits. This model is based on Spin-Transfer Torque (STT) writing approach. This very promising approach should constitute the second generation of MRAM switching technology; it features small switching current (~120uA) and high programming speed (<1ns). The macro-model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform with Spectre 5.0.32 simulator. Many experimental parameters are integrated in this model to improve the simulation accuracy. So, the model can efficiently be used to design hybrid Magnetic CMOS circuits.

A high-performance CMOS-SOI antenna switch for the 2.5-5-GHz band

Abstract: Taking full advantage of the high resistivity substrate and underlying oxide of silicon-on-insulator (SOI) technology, a high-performance CMOS single-pole double-throw (SPDT) T/R switch for Bluetooth class-II applications has been designed and fabricated in a partially depleted 0.25-/spl mu/m SOI process. To compare the influence on losses and isolation of the substrate resistivity, the switch has been integrated above standard and high resistivity (20 /spl Omega//spl middot/cm and 1 k/spl Omega//spl middot/cm) substrates. The switch over the standard resistivity substrate exhibits 1 dB of insertion loss and 45dB of isolation at 2.4 GHz. With the high resistivity substrate, the overall performances are strongly improved until 0.7-dB insertion loss and a 54-dB isolation at 2.4 GHz. At 5 GHz, the switch over the high resistivity substrate keeps insertion loss and isolation at 1 and 46 dB, respectively. In both cases, the measured 1-dB input compression point is 12 dBm. The targeted Bluetooth class-II specifications have been fully fitted.

Secure Memory Accesses on Networks-on-Chip

Abstract: Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses security aspects related to network-on-chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based multiprocessor systems, we focus on the topic, not yet thoroughly faced, of data protection. In this paper, we present a secure NoC architecture composed of a set of data protection units (DPUs) implemented within the network interfaces. The run-time configuration of the programmable part of the DPUs is managed by a central unit, the network security manager (NSM). The DPU, similar to a firewall, can check and limit the access rights (none, read, write, or both) of processors accessing data and instructions in a shared memory - in particular distinguishing between the operating roles (supervisor/user and secure/unsecure) of the processing elements. We explore different alternative implementations for the DPU and demonstrate how this unit does not affect the network latency if the memory request has the appropriate rights. We also focus on the dynamic updating of the DPUs to support their utilization in dynamic environments, and on the utilization of authentication techniques to increase the level of security.

Transformer for integrated circuits

Abstract: A invention provides a transformer for use in integrated circuits, comprising four layers of conductive lines, separated from each other by first, second and third insulating layers. First conductive vias traverse the second insulating layer to connect said second and third pluralities of conducting lines, to form a first winding. Second conductive vias traverse the first, second and third insulating layers to connect said first and fourth pluralities of conducting lines to form a second winding, about and approximately concentric with said first winding.