STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Probability Distributions of Correlation and Differentials in Block Ciphers

Abstract: We study the probability distributions of difference propagation probabilities and input- output correlations for functions and block ciphers of given dimensions, for several of them for the first time. We show that these parameters have distributions that are well-studied in the field of probability such as the normal, Poisson and extreme value distributions. The results of this paper can be used to estimate how much effort will be required to generate functions satisfying certain criteria. The distributions we derive for block ciphers illustrate the significant difference between fixed-key parameters and averaged parameters.

Mixed parallel-dichotomic serial sensing method for sensing multiple-levels non-volatile memory cells, and sensing circuit actuating such method

Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 n (n>=Z) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a discrete set of m distinct cell current values, each cell current value corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current with a prescribed number of reference currents having values comprised between a minimum value and a maximum value of said discrete set of m cell current values and dividing said discrete set of m cell current values in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current belongs; repeating step (a) for the sub-set of cell current values to which the cell current belongs, until the sub-set of cell current values to which the cell current belongs comprises only one cell current value, which is the value of the current of the memory cell to be sensed.

Modal analysis and dynamic responses of board level drop test

Abstract: Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. In this paper, comprehensive dynamic responses of printed circuit boards (PCBs) and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. Control and monitoring of dynamic responses are very important to ensure consistent test results and understand the mechanical behaviors, as they are closely related to solder joint failure mechanisms. The effects of test variables, such as drop height, number of PCB mounting screws, tightness of screws, and number of felt layers, are studied by comparing and analyzing the dynamic responses.

A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology

Abstract: A 4 Mb embedded phase change memory macro has been developed in a 90 nm 6-ML CMOS technology. The storage element has been integrated using 3 additional masks with respect to process baseline. The cell selector is implemented by a standard LV nMOS device, achieving a cell size of 0.29 μm2. A dual-voltage row decoder and a double-path column decoder are introduced, enabling a completely low voltage read operation. A 20b-parallelism write scheme is embedded in the digital controller in order to maximize throughput. In alternative, a power-saving low-parallelism write algorithm can be employed. The macro features a 1.2 V 12 ns read access time and a write throughput of 1 MB/s. Set and reset current distributions showing a good read window are presented and robust reliability results are demonstrated.

Apparatus for at-speed testing, in inter-domain mode, of a multi-clock-domain digital integrated circuit according to BIST or SCAN techniques

Abstract: An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions and freeing the designer to implement his RTL code, respecting only generally few mandatory rules identified by the DFT engineer Such an embodiment is achieved by introducing in the test circuit an embodiment of an additional functional logic circuit block, named “inter-domain on chip clock controller” (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC), of the different clock domains The icOCC actuates synchronization among the different OCCs that source the test clock signals coming from an external ATE or ATPG tool and from internal at-speed test clock generators to the respective circuitries of the distinct clock domains Scan structures like the OCCs, scan chain, etc, may be instantiated at gate pre-scan level, with low impact onto the functional RTL code written by the designer