scispace - formally typeset
Search or ask a question
Institution

STMicroelectronics

CompanyGeneva, Switzerland
About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.


Papers
More filters
Proceedings ArticleDOI
06 Sep 2009
TL;DR: A non-invasive fault model based on the effects of underfeeding the power supply of an ARM general purpose CPU is described and proposed and mount attacks on implementations of the RSA primitives.
Abstract: Fault injection attacks are a powerful tool to exploit implementative weaknesses of robust cryptographic algorithms. The faults induced during the computation of the cryptographic primitives allow to extract pieces of information about the secret parameters stored into the device using the erroneous results. Various fault induction techniques have been researched, both to make practical several theoretical fault models proposed in open literature and to outline new kinds of vulnerabilities. In this paper we describe a non-invasive fault model based on the effects of underfeeding the power supply of an ARM general purpose CPU. We describe the methodology followed to characterize the fault model on an ARM9 microprocessor and propose and mount attacks on implementations of the RSA primitives.

91 citations

Patent
Pierre Rault1
04 Jun 1996
TL;DR: In this article, a power conversion circuit for providing a rectified supply voltage to an output capacitor is described. But it does not specify a power factor correction circuit, and it is not known whether the output voltage of the PFC can exceed a predetermined threshold.
Abstract: A power conversion circuit for providing a rectified supply voltage to an output capacitor. The power conversion circuit includes: a rectifying circuit; a power factor correction circuit; a resistor for limiting inrush current, the resistor being operatively connected between the rectifying circuit and the power factor correction circuit, the capacitor being connected to the output of this power factor correction circuit; and a switch that is operatively connected for short circuiting the resistor, the output capacitor being connected across the output terminals of the power factor correction circuit, the switch being activated when the output voltage of the power factor correction circuit exceeds a predetermined threshold.

91 citations

Journal ArticleDOI
TL;DR: The Homeplug AV2 system architecture is introduced and the technical details of the key features at both the PHY and MAC layers are described and the HomePlug AV2 performance is assessed, through simulations reproducing real home scenarios.
Abstract: HomePlug AV2 is the solution identified by the HomePlug Alliance to achieve the improved data rate performance required by the new generation of multimedia applications without the need to install extra wires. Developed by industry-leading participants in the HomePlug AV Technical Working Group, the HomePlug AV2 technology provides Gigabit-class connection speeds over the existing AC wires within home. It is designed to meet the market demands for the full set of future in-home networking connectivity. Moreover, HomePlug AV2 guarantees backward interoperability with other HomePlug systems. In this paper, the HomePlug AV2 system architecture is introduced and the technical details of the key features at both the PHY and MAC layers are described. The HomePlug AV2 performance is assessed, through simulations reproducing real home scenarios.

91 citations

Journal ArticleDOI
TL;DR: In this paper, the effect of the growth process on the formation of defects in the hetero-epitaxial 3C-SiC film and the possible path for defects reduction has been reported.

91 citations

Proceedings ArticleDOI
09 Oct 2009
TL;DR: In this article, a 32×32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130nm imaging process is presented.
Abstract: We report the design and characterisation of a 32×32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50µm pitch TDC array exhibits a minimum time resolution of 50ps, with accuracy of ±0.5 LSB DNL and 2.4 LSB INL. Process, voltage and temperature compensation (PVT) is achieved by locking the array to a stable external clock. The resulting time correlated pixel array is a viable candidate for single photon counting (TCSPC) applications such as fluorescent lifetime imaging microscopy (FLIM), nuclear or 3D imaging and permits scaling to larger array formats.

90 citations


Authors

Showing all 17185 results

NameH-indexPapersCitations
Bharat Bhushan116127662506
Albert Polman9744542985
G. Pessina8482830807
Andrea Santangelo8388629019
Paolo Mattavelli7448219926
Daniele Ielmini6836716443
Jean-François Carpentier6245914271
Robert Henderson5844013189
Bruce B. Doris5660412366
Renato Longhi551778644
Aldo Romani5442511513
Paul Muralt5434412694
Enrico Zanoni5370513926
Gaudenzio Meneghesso5170312567
Franco Zappa502749211
Network Information
Related Institutions (5)
Intel
68.8K papers, 1.6M citations

92% related

Motorola
38.2K papers, 968.7K citations

91% related

Samsung
163.6K papers, 2M citations

90% related

NEC
57.6K papers, 835.9K citations

89% related

Toshiba
83.6K papers, 1M citations

89% related

Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
202225
2021560
2020798
2019952
2018948
2017781