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Institution

STMicroelectronics

CompanyGeneva, Switzerland
About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.


Papers
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Patent
01 Aug 1998
TL;DR: In this article, a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory, and a partition indicator is allocated to each process identifying which of the cache partitions is to be used for hold items for use in the execution of that process.
Abstract: A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

89 citations

Patent
28 Jan 1994
TL;DR: In this paper, a base cell for a CMOS gate array is disclosed, which utilizes cutoff transistor isolation by way of separate outer electrodes for the p-channel and n-channel sides, so that the diffused regions are disposed at the edges of the cell to be shared with adjacent cells.
Abstract: A base cell for a CMOS gate array is disclosed, which utilizes cutoff transistor isolation. The disclosed cell implements the cutoff transistor isolation by way of separate outer electrodes for the p-channel and n-channel sides, so that p-type and n-type diffused regions are disposed at the edges of the cell to be shared with adjacent cells. The disclosed cell further includes a pair of inner electrodes which extend over both the n-type and p-type active regions. This construction enables the use of cutoff isolation techniques, but also provides the ability to implement transmission gate style latches via the common complementary gate inner electrodes. Greater efficiency of silicon area, improved utilization, and reduced input loading and active power dissipation result from an integrated circuit incorporate the disclosed cells.

89 citations

Journal ArticleDOI
01 Mar 1997
TL;DR: An extensive survey of trends in embedded processor use with an emphasis on emerging applications in wireless communication, multimedia, and general telecommunications and the importance of application-specific instruction-set processors (ASIPs) in high-volume, low cost applications is presented.
Abstract: We present an extensive survey of trends in embedded processor use with an emphasis on emerging applications in wireless communication, multimedia, and general telecommunications. We demonstrate the importance of application-specific instruction-set processors (ASIPs) in high-volume, low cost applications. We also examine some of the underlying trends of the applications in which embedded processors are used. This is followed by a description of embedded software development tool requirements. High-performance software compilation emerges as a key requirement. Finally, specific industrial case studies of products in MPEG, videophone, and low-cost digital signal processor (DSP) applications are used to illustrate the architecture design tradeoffs, and highlight specific tool requirements. A companion paper (Goosens et al., 1997) presents a comprehensive survey of embedded software development tools, focusing mostly on retargetable software compilation.

89 citations

Proceedings ArticleDOI
02 Dec 2017
TL;DR: In this paper, Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs are compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options.
Abstract: This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs Key technological challenges will be discussed and recent research results presented Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization

89 citations

Proceedings ArticleDOI
04 Dec 2009
TL;DR: In this article, a two-phase interleaved LLC resonant converter is proposed that employs a current-controlled inductor to adjust the resonance frequency of one module, thus compensating for component mismatch.
Abstract: Multi-phase interleaved converters represent interesting solutions in terms of reduced current rating of each module, reduction of input and output current ripples, and possibility of redundancy. However, when attempt to interleave resonant converters operating at the same switching frequency, the resonant components' tolerance can cause severe current unbalance between them. In this paper, a two-phase interleaved LLC resonant converter is proposed that employs a current-controlled inductor to adjust the resonance frequency of one module, thus compensating for component mismatch. Experimental results of a prototype rated at 24V-12A output are presented, confirming the theoretical forecasts.

88 citations


Authors

Showing all 17185 results

NameH-indexPapersCitations
Bharat Bhushan116127662506
Albert Polman9744542985
G. Pessina8482830807
Andrea Santangelo8388629019
Paolo Mattavelli7448219926
Daniele Ielmini6836716443
Jean-François Carpentier6245914271
Robert Henderson5844013189
Bruce B. Doris5660412366
Renato Longhi551778644
Aldo Romani5442511513
Paul Muralt5434412694
Enrico Zanoni5370513926
Gaudenzio Meneghesso5170312567
Franco Zappa502749211
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
202225
2021560
2020798
2019952
2018948
2017781