STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

A method for forming planarized shallow trench isolation in an integrated circuit and a structure formed thereby

Abstract: A method for forming isolation structures in an integrated circuit, and the structures so formed, are disclosed. After definition of active regions of the surface is accomplished by provision of masking layers, recesses are etched into the exposed locations, to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material, are disposed along the sidewalls of the recesses, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon then forms a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface. According to an alternative embodiment, the formation of the sidewall spacers may be done in such a manner that narrower recesses remain filled with the material of the sidewall spacers.

UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency

Abstract: UTBB FD-SOI technology has become mainstream within STMicroelectronics, with the objective to serve a wide spectrum of mobile multimedia products. This breakthrough technology brings a significant improvement in terms of performance and power saving, complemented by an excellent responsiveness to power management design techniques for energy efficiency optimization. The symbiosis between process and design is key in this achievement enabling to provide already at 28nm node a real differentiation in terms of flexibility, cost and energy efficiency with respect to any process available on the market.

Capacitive -inductive touch screen

Abstract: A touch screen uses a combination of capacitive sensing and inductive sensing applied to the same sensor pattern. A capacitive sensor uses the electric field formed by the columns and rows of the sensor matrix. An inductive sensor uses the magnetic field formed by current flowing in column and row lines to induce an inductive pen. Using the same sensor lines, the magnetic field created by the oscillating inductive pen is detected. Both methods require no moving elements in the sensor and it is possible to combine both method of detections in the same sensor pattern. Using switch matrices, the sensor lines are operated in an open loop fashion for the capacitive detection mode, and are operated in a closed loop fashion for the inductive detection mode.

A 1.2V, 140GHz receiver with on-die antenna in 65nm CMOS

Abstract: This paper presents a 1.2 V, 100 mW, 140 GHz receiver with on-die antenna in a 65 nm General Purpose (GP) CMOS process with digital back-end. The receiver has a conversion loss of 15-19 dB in the 100-140 GHz range with 102 GHz LO, and occupies a die area of only 580 mum times 700 mum including pads. The LNA achieves 8 dB gain at 140 GHz, 10 GHz bandwidth, at least -1.8 dBm of saturated output power, and maintains 3 dB gain at 125 degC. The on-chip antenna, which meets all density fill requirements of 65 nm CMOS, has -25 dB gain, and occupies 180 mum times 100 mum of die area. Additionally, design techniques which maximize the millimeter-wave performance of CMOS devices are discussed.

A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput

Abstract: A 4Gb 2b/cell NAND flash memory designed in a 90nm CMOS technology incorporates a 25MHz BCH ECC architecture, correcting up to 5 errors over a flexible data field (1B to 2102B). Two alternative Chien circuits are used depending on the number of errors (1 to 5) thus minimizing latency time. ECC area overhead is less than 1%