STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Method of forming isolated regions of oxide

Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process

Abstract: For the first time, both GAA and bulk devices were shown to be operational on the same chip. Not all issues have been solved yet (gate materials, access resistance) but already the first-try results are very encouraging: I/sub on/=170 /spl mu/A//spl mu/m@1.2 V and gate oxide of 20 /spl Aring/. Thanks to the GAA intrinsic immunity to SCE, its DIBL was as small as 10 mV compared with 600 mV on bulk control devices. Calibrating a 2D simulator on this electrical data, the performance of the GAA was estimated to be at least 1500 /spl mu/A//spl mu/m@ 1 V with comfortable gate oxide of 20 /spl Aring/, once having corrected for the large R/sub access/ (/spl sim/3000 /spl Omega/), that was simply due to non-optimal mask layout used in this first device realization.

11.5 A time-correlated single-photon-counting sensor with 14GS/S histogramming time-to-digital converter

Abstract: Time-correlated single photon counting (TCSPC) is a photon-efficient technique to record ultra-fast optical waveforms found in numerous applications such as time-of-flight (ToF) range measurement (LIDAR) [1], ToF 3D imaging [2], scanning optical microscopy [3], diffuse optical tomography (DOT) and Raman sensing [4]. Typical instrumentation consists of a pulsed laser source, a discrete detector such as an avalanche photodiode (APD) or photomultiplier tube (PMT), time-to-digital converter (TDC) card and a FPGA or PC to assemble and compute histograms of photon time stamps. Cost and size restrict the number of channels of TCSPC hardware. Having few detection and conversion channels, the technique is limited to processing optical waveforms with low intensity, with less than one returned photon per laser pulse, to avoid pile-up distortion [4]. However, many ultra-fast optical waveforms exhibit high dynamic range in the number of photons emitted per laser pulse. Examples are signals observed at close range in ToF with multiple reflections, diffuse reflected photons in DOT or local variations in fluorescent dye concentration in microscopy. This paper provides a single integrated chip that reduces conventional TCSPC pile-up mechanisms by an order of magnitude through ultra-parallel realizations of both photon detection and time-resolving hardware. A TDC architecture is presented which combines the two step iterated TCSPC process of time-code generation, followed by memory lookup, increment and write, into one parallel direct-to-histogram conversion. The sensor achieves 71.4ps resolution, over 18.85ns dynamic range, with 14GS/s throughput. The sensor can process 1.7Gphoton/s and generate 21k histograms/s (with 4.6μs readout time), each capturing a total of 1.7kphotons in a 1μs exposure.

Overview of the JET preparation for deuterium–tritium operation with the ITER like-wall

Abstract: For the past several years, the JET scientific programme (Pamela et al 2007 Fusion Eng. Des. 82 590) has been engaged in a multi-campaign effort, including experiments in D, H and T, leading up to 2020 and the first experiments with 50%/50% D–T mixtures since 1997 and the first ever D–T plasmas with the ITER mix of plasma-facing component materials. For this purpose, a concerted physics and technology programme was launched with a view to prepare the D–T campaign (DTE2). This paper addresses the key elements developed by the JET programme directly contributing to the D–T preparation. This intense preparation includes the review of the physics basis for the D–T operational scenarios, including the fusion power predictions through first principle and integrated modelling, and the impact of isotopes in the operation and physics of D–T plasmas (thermal and particle transport, high confinement mode (H-mode) access, Be and W erosion, fuel recovery, etc). This effort also requires improving several aspects of plasma operation for DTE2, such as real time control schemes, heat load control, disruption avoidance and a mitigation system (including the installation of a new shattered pellet injector), novel ion cyclotron resonance heating schemes (such as the threeions scheme), new diagnostics (neutron camera and spectrometer, active Alfven eigenmode antennas, neutral gauges, radiation hard imaging systems…) and the calibration of the JET neutron diagnostics at 14 MeV for accurate fusion power measurement. The active preparation of JET for the 2020 D–T campaign provides an incomparable source of information and a basis for the future D–T operation of ITER, and it is also foreseen that a large number of key physics issues will be addressed in support of burning plasmas.

Efficient and First-Order DPA Resistant Implementations of Keccak

Abstract: In October 2012 NIST announced that the SHA-3 hash standard will be based on Keccak. Besides hashing, Keccak can be used in many other modes, including ones operating on a secret value. Many applications of such modes require protection against side-channel attacks, preferably at low cost. In this paper, we present threshold implementations (TI) of Keccak with three and four shares that build further on unprotected parallel and serial architectures. We improve upon earlier TI implementations of Keccak in the sense that the latter did not achieve uniformity of shares. In our proposals we do achieve uniformity at the cost of an extra share in a four-share version or at the cost of injecting a small number of fresh random bits for each computed round. The proposed implementations are efficient and provably secure against first-order side-channel attacks.