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Institution

STMicroelectronics

CompanyGeneva, Switzerland
About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Transistor & Signal. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.


Papers
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Proceedings ArticleDOI
01 Dec 2010
TL;DR: In this paper, the authors highlight some of the recent advancements in next generation eWLB technologies including multi-RDL, thin e-WLB and extra large eWLP as well as double-side with vertical interconnection.
Abstract: Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. “Fan-in” (FI)-WLP typically has a limitation to be less than 6x6mm in order to pass board level reliability requirements such as drop test and temperature cycle due to the mismatch of Si material properties to the PCB. However, the “Fan-out” (FO)-WLP, has been developed and introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. The most prominent type of FO-WLP is the eWLB technology (embedded Wafer Level Ball Grid Array). Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in next generation eWLB technologies including multi-RDL, thin eWLB and extra large eWLB as well as double-side with vertical interconnection. These key technologies of next generation eWLB enable 3D eWLB applications such as SoW (SiP on Wafer) and 3D SiP. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. The process flow of next generation eWLB fabrication, assembly and packaging challenges will be discussed. This paper will also present some of the achievements in package reliability, mechanical characterization and performance.

79 citations

Journal ArticleDOI
TL;DR: In this article, a comprehensive dynamic responses of printed circuit board (PCB) and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method.
Abstract: Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e., crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints, dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when the PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross section and dye penetration tests

79 citations

Journal ArticleDOI
TL;DR: The attenuation of longitudinal acoustic phonons up to frequencies nearing $250\phantom{\rule{0.3em}{0ex}}\mathrm{GHz}$ was measured in vitreous silica with a picosecond optical technique as discussed by the authors.
Abstract: The attenuation of longitudinal acoustic phonons up to frequencies nearing $250\phantom{\rule{0.3em}{0ex}}\mathrm{GHz}$ is measured in vitreous silica with a picosecond optical technique. By taking advantage of interferences on the probe beam, difficulties encountered in early pioneering experiments are alleviated. Sound damping at $250\phantom{\rule{0.3em}{0ex}}\mathrm{GHz}$ and room temperature is consistent with relaxation dominated by anharmonic interactions with the thermal bath, extending optical Brillouin scattering data. Our result is at variance with claims of a recent deep-UV experiment which reported a rapid damping increase beyond $100\phantom{\rule{0.3em}{0ex}}\mathrm{GHz}$. A comprehensive picture of the frequency dependence of sound attenuation in $v\text{\ensuremath{-}}\mathrm{Si}{\mathrm{O}}_{2}$ can be proposed.

79 citations

Proceedings ArticleDOI
01 Sep 2003
TL;DR: A built in self-diagnosis of EEPROM memory cells, based on threshold voltage extraction is presented and complementary information is proposed to improve the classical memory diagnosis.
Abstract: Knowing, that the threshold voltage of the EEPROM memory cells is a key parameter to determine the overall performance of the memory, a build in structure to extract this information is a very relevant choice to fast diagnose failure in the memory. Thus, the objective of this paper is to present a built in self-diagnosis of EEPROM memory cells, based on threshold voltage extraction. In order to extract the threshold voltage, the modified circuit and the associated test sequence are presented. Based on the threshold voltage extraction, complementary information is proposed to improve the classical memory diagnosis

79 citations

Journal ArticleDOI
TL;DR: In this article, a continuous compact model for the drain current, including short-channel effects and carrier quantization in Double-Gate MOSFETs, is developed, particularly well-adapted to ultra-scaled devices, with short channel lengths and ultra-thin silicon films.
Abstract: A continuous compact model for the drain current, including short-channel effects and carrier quantization in Double-Gate MOSFET is developed. The model is particularly well-adapted to ultra-scaled devices, with short channel lengths and ultra-thin silicon films. An extensive comparison step with 2D quantum numerical results fully validates the model. The model is also shown to reproduce with an excellent accuracy experimental drain current in Double-Gate devices. Finally, the drain current model has been supplemented by a node charge model and the resulting DG model has been successfully implemented in Eldo IC analog simulator, demonstrating the application of the model to circuit simulation.

79 citations


Authors

Showing all 17185 results

NameH-indexPapersCitations
Bharat Bhushan116127662506
Albert Polman9744542985
G. Pessina8482830807
Andrea Santangelo8388629019
Paolo Mattavelli7448219926
Daniele Ielmini6836716443
Jean-François Carpentier6245914271
Robert Henderson5844013189
Bruce B. Doris5660412366
Renato Longhi551778644
Aldo Romani5442511513
Paul Muralt5434412694
Enrico Zanoni5370513926
Gaudenzio Meneghesso5170312567
Franco Zappa502749211
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
202225
2021560
2020798
2019952
2018948
2017781