Technological Educational Institute of Western Macedonia

About: Technological Educational Institute of Western Macedonia is a based out in . It is known for research contribution in the topics: Symplectic geometry & Numerical integration. The organization has 291 authors who have published 522 publications receiving 7682 citations. The organization is also known as: TEI of West Macedonia & TEI of Western Macedonia.

Resource and Reserve estimation for a marble quarry using quality indicators

Abstract: this paper concerns the Platanotopos quarry of Iktinos Hellas SA (Figure 1) – similar procedures are applied to the other quarries of the company. Specialized mine planning software (Maptek Vulcan Quarry Modeller) was used in all estimation and reporting stages. Data was provided by Iktinos Hellas SA personnel, including sample quality characterization. A technical report was issued on behalf of Iktinos Hellas SA (Kapageridis, 2015). Similar computerized estimation efforts are reported by Forlani and Pinto (2000), Careddu, Siotto, and Tuveri (2010), and Abdollahisharif et al. (2012).

Characterisation of Mycenaean and matt-painted pottery from Alani, ancient upper Macedonia, Greece

Abstract: Διάφορeς αναλυτικές μέθοδοι eφαρμόστηκαν για τη μeλέτη αρχαίων κeραμικών από την Αιανή, αρχαία Ανω Μακeδονία. Όστρακα μυκηναϊκής και αμαυρόχρωμης κeραμικής ηλικίας Ύστeρης Eποχής Χαλκού συλλέχθηκαν και αναλύθηκαν μe τη βοήθeια της πeριθλασ ι μeτρίας ακτινών Χ (XRD), της φασματοσκοπίας φθορισμού ακτινών Χ (XRF) και του «πeριβαλλοντικού» ηλeκτρονικού μικροσκοπίου σάρωσης (ESEM). Τα μορφολογικά χαρακτηριστικά, η χημική και η ορυκτολογική σύσταση των αναλυθέντων οστράκων υποδηλώνουν την κατασκeυή των κeραμικών αυτών σe τοπικά eργαστήρια της αρχαίας Αιανής, eνώ υποστηρίζουν και την υπόθeση των αρχαιολόγων για την συνύπαρξη μυκηναϊκών και δωρικών eργαστηρίων κeραμικής στην πeριοχή αυτή, κατά τη διάρκeια της Ύστeρης Eποχής Χαλκού

High-level Synthesis Integrated Verification

Abstract: It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For the very complex contemporary chips, this may prove prohibitive for the IC to arrive at the correct time in the market and therefore, valuable sales share may be lost by the developing industry. This problem is deteriorated by the fact that most of conventional verification flows are highly repetitive and a great proportion of the project time is spent on last-moment simulations. In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author. Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. This paper is supported by strong experimental work with 3-4 popular design synthesis and verification that proves the principles of our methodology.

Formal generation of synthesizable RTL from regular programs

Abstract: The complexity of the contemporary digital circuits and systems, determines the need for higher specification abstraction and automatic circuit synthesis techniques to be adopted. A prototype high level synthesis framework is presented here, that automatically generates synthesizable RTL code from unaltered, high level programs. The framework is developed using compiler-generator and logic programming (thus formal) techniques, and it utilizes a patented intermediate compilation format to retain the algorithmic semantics of the source programs and allow for compiler transformations. The synthesis framework is evaluated via statistics from a number of real-life applications. The performance optimization of the compiled applications, including an MPEG engine, underlines the quality of the prototype design framework.