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Institution

Teradyne

CompanyBoston, Massachusetts, United States
About: Teradyne is a company organization based out in Boston, Massachusetts, United States. It is known for research contribution in the topics: Automatic test equipment & Signal. The organization has 828 authors who have published 999 publications receiving 15695 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, the OPAL equation-of-state (EOS) and opacity data were extended to include low-mass stars with mass less than 0.1 M. The EOS part of that effort now is complete, and the results are described herein.
Abstract: We are in the process of updating and extending the OPAL equation-of-state (EOS) and opacity data to include low-mass stars. The EOS part of that effort now is complete, and the results are described herein. The new data cover main-sequence stars having mass � 0.1 M� . As a result of the more extreme matter conditions encountered with low-mass stars, we have added new physics. The electrons are now treated as relativistic, and we have improved our treatment of molecules. We also consider the implications of the new results for helioseismology.

920 citations

Patent
27 Jun 1996
TL;DR: In this paper, electrical connectors are provided with shield units each having a plurality of shields joined by a bridge, and the shield units are mounted in a base stiffened by means apertured to carry mounting ear means.
Abstract: Electrical connectors are provided with shield units each having a plurality of shields joined by a bridge. Preferably the shield units are mounted in a base stiffened by means apertured to carry mounting ear means.

358 citations

Patent
Antonios E. Prentakis1
02 Dec 1986
TL;DR: In this paper, a support structure with associated with it a predetermined wafer engagement position at which wafers can be engaged by the processing machine is used for loading and unloading of wafer, and the flat surfaces of the wafer being parallel to an X-axis and perpendicular to a Z-axis.
Abstract: Apparatus for loading and unloading wafers including a support structure having associated with it a predetermined wafer engagement position at which wafers can be engaged by the processing machine, a temporary storage device mounted on the support structure for storing a wafer in position for pick up, the flat surfaces of the wafer being parallel to an X-axis and perpendicular to a Z-axis, a first wafer engagement member for carrying the wafer on the first engagement member between the temporary storage device and the engagement position, a first X-direction mover mounted on the support structure and operable to move the first engagement member parallel to the X-axis, a second wafer engagement member for carrying the wafer on the second engagement member between the temporary storage device and the engagement position, a second X-direction mover mounted on the support structure and operable to move the second engagement member parallel to the X-axis independent of the first engagement member, a Z-direction mover mounted on the support structure and operable to move the first and second engagement members in the Z-direction, and a controller to cause the first X-direction mover to move the first engagement member parallel to the X-axis toward the engagement position at the same time as or shortly after the second engagement member moves parallel to said X-axis away from the engagement position.

160 citations

Patent
Sepehr Kiani1, Mikhail Khusid1
23 Jul 1999
TL;DR: In this article, an interconnection circuit includes a plated through hole having a plurality of electrically isolated segments with at least one of the plurality of isolated segments coupled to a signal path.
Abstract: An interconnection circuit and related techniques are described. The interconnection circuit includes a plated through hole having a plurality of electrically isolated segments with at least one of the plurality of electrically isolated segments coupled to a signal path and at least one of the electrically isolated segments coupled to ground. With this arrangement, the circuit provides a signal path between a first and a second different layers of a multilayer. By providing one segment as a signal segment and another segment as a ground segment the size and shape of the electrically isolated segments can be selected to provide the interconnection circuit having a predetermined impedance characteristic. The interconnection circuit can thus be impedance matched to circuit board circuits, devices and transmission lines, such as striplines, microstrips and co-planar waveguides. This results in an interconnection circuit which maintains the integrity of relatively high-frequency signals propagating through the interconnection circuit from the first layer to the second layer. The interconnect circuits can be formed by creating distinct conductor paths within the cylindrical plated through-holes using variety of manufacturing techniques including, but not limited to, broaching techniques, electrostatic discharge milling (EDM) techniques and laser etching techniques.

148 citations

Journal ArticleDOI
John R. Day1
TL;DR: A fault-driven algorithm that generates all possible repair solutions for a given bit failure pattern in a redundant RAM, able to generate solutions for any theoretically repairable die that would be deemed unrepairable by existing algorithms.
Abstract: This article describes a fault-driven algorithm that generates all possible repair solutions for a given bit failure pattern in a redundant RAM. Benefits of this approach include the ability to select repair solutions based on userdefined preferences (for example, fewest total elements invoked or fewest rows invoked). Perhaps the greatest advantage of this algorithm is its ability to generate solutions for any theoretically repairable die that would be deemed unrepairable by existing algorithms.

138 citations


Authors

Showing all 830 results

NameH-indexPapersCitations
John H. Lienhard6841918058
Todd Austin5516720607
Alexander H. Slocum444499393
Scott C. Noble30983495
D. R. LaFosse261392555
Tongdan Jin261132326
Thomas S. Cohen24372490
Mark W. Gailus21541851
R. Ryan Vallance20871081
Richard F. Roth18371104
Sepehr Kiani1528672
Frank W. Ciarallo14441066
Brian S. Merrow1434621
Philip T. Stokoe13261238
Ernest P. Walker1222252
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20223
20218
202020
201914
201811
201715