Tripura Institute of Technology

About: Tripura Institute of Technology is a based out in . It is known for research contribution in the topics: Electric power system & Renewable energy. The organization has 63 authors who have published 92 publications receiving 510 citations.

An Inter-Test Cube Bit Stream Connectivity-Optimized X-Filling Approach Aiming Shift Power Reduction

Abstract: Transitions in scan cells bear much impact on the power consumption in scan-based VLSI test systems. X-filling approaches aim to fill don’t care bits of test cube by typically assigning binary values (i.e. either 1s or 0s) in such a way that the mean switching activity gets lessened. We propose here a new X-filling approach named as bit stream connectivity optimization-based X-filling technique, called BSCO—a technique to decrease average shift-in transitions crop up during scan-based testing. In our approach, we have not only considered the shift-in switching activity specific to test vectors but also minimized inter-test cube switching activity by applying BSCO approach. The experimental outcomes attained from the benchmark ISCAS’89 clearly shows that the method is effective for reducing average transitions during scan shift operation.

Source/Drain (S/D) Spacer-Based Reconfigurable Devices-Advantages in High-Temperature Applications and Digital Logic

Abstract: This paper explores source/drain (S/D) spacer technology-based reconfigurable field-effect transistors (RFETs) and a detailed physical insight toward the advantages of using spacer oxide in RFETs for applications involving rapid temperature fluctuations and reduction of circuit delay in contrast to conventional ambipolar FETs and other devices based on band-to-band tunneling (BTBT) such as TFETs. Temperature-based DC, analog and RF performance of gate-all-around (GAA), heterogeneous gate dielectric GAA, SiGe, and full silicon TFETs are compared. Moreover, it is also shown that the propagation delay in logic circuits is reduced for the proposed DG-RFET resulting in more robust and improved circuit performance.

High throughput resource efficient reconfigurable interleaver for MIMO WLAN application.

Abstract: Demand for high-speed wireless broadband internet service is ever increasing. Multiple-input-multiple-output (MIMO) Wireless LAN (WLAN) is becoming a promising solution for such high-speed internet service requirements. This paper proposes a novel algorithm to efficiently model the address generation circuitry of the MIMO WLAN interleaver. The interleaver used in the MIMO WLAN transceiver has three permutation steps involving floor function whose hardware implementation is the most challenging task due to the absence of corresponding digital hardware. In this work, we propose an algorithm with a mathematical background for the address generator, eliminating the need for floor function. The algorithm is converted into digital hardware for implementation on the reconfigurable FPGA platform. Hardware structure for the complete interleaver, including the read address generator and memory module, is designed and modeled in VHDL using Xilinx Integrated Software Environment (ISE) utilizing embedded memory and DSP blocks of Spartan 6 FPGA. The functionality of the proposed algorithm is verified through exhaustive software simulation using ModelSim software. Hardware testing is carried out on Zynq 7000 FPGA using Virtual Input Output (VIO) and Integrated Logic Analyzer (ILA) core. Comparisons with few recent similar works, including the conventional Look-Up Table (LUT) based technique, show the superiority of our proposed design in terms of maximum improvement in operating frequency by 196.83%, maximum reduction in power consumption by 74.27%, and reduction of memory occupancy by 88.9%. In the case of throughput, our design can deliver 8.35 times higher compared to IEEE 802.11n requirement.

Classification of Voltage Security States Using Supervised ANNs

Abstract: This chapter focuses on the application of self-organizing neural networks that are capable of extracting valuable data from their working surroundings. The basic role of self-organization lies in the invention of significant patterns without the intervention of a teaching input. An important aspect of the implementation of such a system is that all adaptations must be based on the data that are accessible locally to the neural connection from the pre- and postsynaptic neuron signals and activations. Self-organization must lead eventually to a state of knowledge that provides useful information concerning the environment from which patterns are drawn. As an alternative to the multilayer perceptron, Kohonen’s self-organizing neural network offers some advantages, particularly in clustering-type applications. Faster learning rate and straightforward interpretation of the classification results make self-organizing map (SOM) an ideal choice for the classification of voltage security states in multi-bus power networks. This chapter describes an artificial neural network-based approach, in which Kohonen’s self-organizing feature map technique has been applied to classify the power system operating states based on their degree of static voltage stability.

Soft Computing Techniques—An Overview

Abstract: This chapter develops a working model of an artificial neuron and introduces neural network architectures, properties, and components. The similarities between biological and artificial neural networks are described along with the architecture of neuron. This chapter also introduces an artificial neural network’s learning process.