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Institution

TSMC

CompanySan Jose, California, United States
About: TSMC is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Layer (electronics) & Gate oxide. The organization has 29808 authors who have published 22185 publications receiving 256094 citations. The organization is also known as: Taiwan Semiconductor Manufacturing Corporation & Taiwan Semiconductor Co., Ltd..


Papers
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Journal ArticleDOI
TL;DR: Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented and the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated.
Abstract: In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use.

922 citations

Journal ArticleDOI
01 Sep 2019-Nature
TL;DR: The opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems are reviewed, and the prospects for computational and non-computational applications are considered.
Abstract: The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the atomic limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technology. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications. Progress in integrating atomically thin two-dimensional materials with silicon-based technology is reviewed, together with the associated opportunities and challenges, and a roadmap for future applications is presented.

804 citations

Patent
08 Mar 2012
TL;DR: In this article, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region, which includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide.
Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.

490 citations

Journal ArticleDOI
TL;DR: Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT/fMAX of 120 GHz/200 GHz.
Abstract: Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT/fMAX of 120 GHz/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB bandwidth >13 GHz, a P 1dB of +6.4 dBm with 7% PAE and a saturated output power of +9.3 dBm at 60 GHz. The LNA represents the first 90-nm CMOS implementation at 60 GHz and demonstrates improvements in noise, gain and power dissipation compared to earlier 60-GHz LNAs in 160-GHz SiGe HBT and 0.13-mum CMOS technologies. It features 14.6 dB gain, an IIP 3 of -6.8 dBm, and a noise figure lower than 5.5 dB, while drawing 16 mA from a 1.5-V supply. The use of spiral inductors for on-chip matching results in highly compact layouts, with the total PA and LNA die areas with pads measuring 0.35times0.43 mm2 and 0.35times0.40 mm2, respectively

463 citations

Patent
09 Mar 2012
TL;DR: In this article, a method for generating a layout for a device having FinFETs from a first layout of the device having planar transistors is presented, where the planar layout is analyzed and corresponding Fin-FET structures are generated in a matching fashion.
Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

457 citations


Authors

Showing all 29809 results

NameH-indexPapersCitations
Chenming Hu119129657264
Lain-Jong Li11362758035
Liwei Lin7168020195
Rashid Bashir7147220140
H.-S. Philip Wong7043420590
Eugene A. Fitzgerald6247617427
David C. Yen6134517988
Shimeng Yu6031215008
J. Kwo5838013533
Minghwei Hong5851514309
Robert Bogdan Staszewski5749112517
Chun Chen5742411788
Jean-Pierre Colinge5745819479
Meikei Ieong541629719
Rita Vos5432710418
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20221
2021440
20201,365
20191,276
2018933
2017906