Varian Associates

About: Varian Associates is a based out in . It is known for research contribution in the topics: Beam (structure) & Wafer. The organization has 2160 authors who have published 2591 publications receiving 46002 citations.

Methods and apparatus for gas-assisted thermal transfer with a semiconductor wafer

Abstract: Methods and apparatus for differential pumping of a thermal transfer gas used to transfer thermal energy between a semiconductor wafer and a platen during processing in a vacuum chamber. Housing structure defines an intermediate region adjacent to and surrounding the platen. The gas, which is introduced into a thermal transfer region behind the wafer, is restricted from flowing into the intermediate region by intimate contact between the wafer and the platen. A clamping ring, which clamps the wafer to the platen, and a bellows coupled between the clamping ring and the housing restrict flow of gas from the intermediate region to the vacuum chamber. The intermediate region is vacuum pumped to a pressure lower than the pressure in the thermal transfer region whereby leakage of the gas into the vacuum chamber is reduced.

Sample container support with coding means

Abstract: A system for injecting sample fluids from a plurality of containers into a sample receiver. The containers are supported on removable racks having a plurality of permanent cam tracks on its lower surface which cooperate with switches to produce binary information identifying the sample rack and sample container location at the sample station.

A study of high-speed normally off and normally on Al 0.5 Ga 0.5 As heterojunction gate GaAs FET's (HJFET)

Abstract: The dc, small-signal microwave, and large-signal switching performance of normally off and normally on Al 0.5 Ga 0.5 As gate heterojunction GaAs field-effect transistors (HJFET) with submicrometer gate lengths are reported. The structure of both types of devices comprises an n-type 1017-cm-3Sn-doped active layer on a Cr-doped GaAs substrate, a p-type 1018-cm-3Ge-doped Al 0.5 Ga 0.5 As gate layer and a p+-type 5 × 1018-cm-3Ge-doped GaAs "contact and cap" layer on the top of the gate. The gate structure is obtained by selectively etching the p+-type GaAs and Al 0.5 Ga 0.5 As. Undercutting of the Al 0.5 Ga 0.5 As layer results in submicrometer gate lengths, and the resulting p+-GaAs overhang is used to self-align the source and the drain with respect to the gate. Normally off GaAs FET's with 0.5- to 0.7-µm long heterojunction gates exhibit maximum available power gains (MAG) of about 9 dB at 2 GHz. Large-signal pulse measurements indicate an intrinsic propagation delay of 40 ps with an arbitrarily chosen 100-Ω drain load resistance in a 50-Ω microstrip circuit. Normally on FET's with submicrometer gate lengths (∼0.6 µm) having a total gate periphery of 300 µm and a corresponding dc transconductance of 20-30 mmhos exhibit a MAG of 9.5 dB at 8 GHz. The internal propagation delay time measured under the same conditions as above is about 20 ps.