Worcester Polytechnic Institute

About: Worcester Polytechnic Institute is a education organization based out in Worcester, Massachusetts, United States. It is known for research contribution in the topics: Population & Data envelopment analysis. The organization has 6270 authors who have published 12704 publications receiving 332081 citations. The organization is also known as: WPI.

Banking credit worthiness: Evaluating the complex relationships

Abstract: In developing economies agriculture and farming play crucial roles for economic sustainable development. Farmer credit risk evaluation is an important issue when determining financial support to farmers, improving agricultural supply chain performance, and ensuring profitability of financial institutions. Credit risk evaluation, or creditworthiness, is not a trivial exercise due to various complexities. Honoring complexity is necessary to effectively evaluate and predict farmer creditworthiness. A methodology using fuzzy rough-set theory and fuzzy C-means clustering is used to evaluate and investigate the complex relationships between farmer characteristics, competitive environmental factors, and farmer credit level. The methodology is detailed using actual bank data from 2044 farmers within China. This empirical methodology generates decision rules that provide insight to more complex relationships than can be found through standard econometric multivariate approaches. A rule-based methodological outcome can be used to predict the creditworthiness of farmers and to aid in agricultural loan decision making. Prediction accuracy of the rule-base was 81.16%. A central finding is that education and skills related characteristics are important for determining farmer credit-worthiness. Other implications are presented along with study limitations and future research directions.

Fast arithmetic for public-key algorithms in Galois fields with composite exponents

Abstract: The article describes a novel class of arithmetic architectures for Galois fields GF(2/sup k/). The main applications of the architecture are public key systems which are based on the discrete logarithm problem for elliptic curves. The architectures use a representation of the field GF(2/sup k/) as GF((2/sup n/)/sup m/), where k=n/spl middot/m. The approach explores bit parallel arithmetic in the subfield GF(2/sup n/) and serial processing for the extension field arithmetic. This mixed parallel-serial (hybrid) approach can lead to fast implementations. As the core module, a hybrid multiplier is introduced and several optimizations are discussed. We provide two different approaches to squaring. We develop exact expressions for the complexity of parallel squarers in composite fields, which can have a surprisingly low complexity. The hybrid architectures are capable of exploring the time-space trade-off paradigm in a flexible manner. In particular, the number of clock cycles for one field multiplication, which is the atomic operation in most public key schemes, can be reduced by a factor of n compared to other known realizations. The acceleration is achieved at the cost of an increased computational complexity. We describe a proof-of-concept implementation of an ASIC for multiplication and squaring in GF((2/sup n/)/sup m/), m variable.

Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC"

Abstract: Self-calibration in approximately 10 000 conversions is demonstrated in a 16-bit, 1-MS/s algorithmic analog-to-digital converter (ADC). Continuous digital background calibration is enabled by introduction of a \"split ADC\" architecture, in which the die area of a single ADC design is split into two independent converters, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for the background calibration process. Since both ADCs convert the same input, when correctly calibrated their outputs should be equal and the difference should be zero. Any nonzero difference provides information to an error estimation process which adjust calibration parameters in each ADC. For the specific realization of an algorithmic ADC described in this paper, a multiple residue mode amplifier is used to ensure different decision trajectories and provide valid calibration information. The analog sub-system of the ADC is implemented in 0.25-/spl mu/m CMOS, consumes 105 mW, and has a die size of 1.2 mm /spl times/ 1.4 mm.