Worcester Polytechnic Institute

About: Worcester Polytechnic Institute is a education organization based out in Worcester, Massachusetts, United States. It is known for research contribution in the topics: Computer science & Population. The organization has 6270 authors who have published 12704 publications receiving 332081 citations. The organization is also known as: WPI.

Elliptic curve cryptography on smart cards without coprocessors

Abstract: This contribution describes how an elliptic curve cryptosystem can be implemented on very low cost microprocessors with reasonable performance. We focus in this paper on the Intel 8051 family of microcontrollers popular in smart cards and other cost-sensitive devices. The implementation is based on the use of the finite field GF((28 – 17)17) which is particularly suited for low end 8-bit processors. Two advantages of our method are that subfield modular reduction can be performed infrequently, and that an adaption of Itoh and Tsujii’s inversion algorithm is used for the group operation. We show that an elliptic curve scalar multiplication with a fixed point, which is the core operation for a signature generation, can be performed in a group of order approximately 2134 in less than 2 seconds Unlike other implementations, we do not make use of curves defined over a subfield such as Koblitz curves.

An FPGA implementation and performance evaluation of the Serpent block cipher

Abstract: With the expiration of the Data Encryption Standard (DES) in 1998, the Advanced Eneryption Standard (AES) development process is well underway. It is hoped that the result of the AES process will be the specification of a new non-classified encryption algorithm that will have the global acceptance achieved by DES as well as the capability of long-term protection of sensitive information. The technical analysis used in determining which of the potential AES candidates will be selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of an FPGA implementation of Serpent, one of the Advanced Encryption Standard candidate algorithms. Multiple architecture options of the Serpent algorithm will be explored with a strong focus being placed on a high speed implementation within an FPGA in order to support security for current and future high bandwidth applications. One of the main findings is that Serpent can be implemented with encryption rates beyond 4 Gbit/s on current FPGAs.

Differential template attacks on PUF enabled cryptographic devices

Abstract: In this paper we provide the first practical attacks on software implementations of fuzzy extractors (FEs). The significance of these attacks stem from the fact that FEs are becoming an essential building block in the implementations of physical unclonable function (PUF) enabled devices. In fact, almost every single implementation of PUFs heavily relies on using a FE. Our attacks exploit the information leaked through the power side-channel in the initial stages of error correction and can be used to recover the FE input which would essentially mean cloning the PUF device. More specifically, our attacks target the initial step in the syndrome decoding phase of BCH and Reed-Solomon (RS) decoder implementations where the input (PUF response) is read. We report two attacks: a simple power analysis (SPA) attack where we make use of conditional checks in a naive implementation to recover the PUF response by simply observing time shifts in the power consumption profile. In our second attack, we assume all conditional executions are removed making the device secure against SPA attacks. Instead, we mount a new kind of template attack on a two instruction sequence to recover the FE input (or PUF output).

Sleep Monitoring Based on a Tri-Axial Accelerometer and a Pressure Sensor

Abstract: Sleep disorders are a common affliction for many people even though sleep is one of the most important factors in maintaining good physiological and emotional health. Numerous researchers have proposed various approaches to monitor sleep, such as polysomnography and actigraphy. However, such approaches are costly and often require overnight treatment in clinics. With this in mind, the research presented here has emerged from the question: “Can data be easily collected and analyzed without causing discomfort to patients?” Therefore, the aim of this study is to provide a novel monitoring system for quantifying sleep quality. The data acquisition system is equipped with multimodal sensors, including a three-axis accelerometer and a pressure sensor. To identify sleep quality based on measured data, a novel algorithm, which uses numerous physiological parameters, was proposed. Such parameters include non-REM sleep time, the number of apneic episodes, and sleep durations for dominant poses. To assess the effectiveness of the proposed system, three participants were enrolled in this experimental study for a duration of 20 days. From the experimental results, it can be seen that the proposed monitoring system is effective for quantifying sleep quality.