Showing papers in "ACM Journal on Emerging Technologies in Computing Systems in 2007"
TL;DR: A new generation of predictive technology model (PTM) is developed, covering emerging physical effects and alternative structures, based on physical models and early stage silicon data, and correctly captures process sensitivities in the nanometer regime.
Abstract: A predictive MOSFET model is critical for early circuit design research. In this work, a new generation of Predictive Technology Model (PTM) is developed, covering emerging physical effects and alternative structures, such as the double-gate device (i.e., FinFET). Based on physical models and early stage silicon data, PTM of bulk and double-gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm. By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10p for both NMOS and PMOS. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. PTM is available online at http://www.eas.asu.edu/~ptm.
TL;DR: This work forms the placement problem of digital microfluidic biochips with a tree-based topological representation, called T-tree, and considers the defect tolerant issue to avoid to use defective cells due to fabrication.
Abstract: Droplet-based microfluidic biochips have recently gained much attention and are expected to revolutionize the biological laboratory procedures. As biochips are adopted for the complex procedures in molecular biology, its complexity is expected to increase due to the need of multiple and concurrent assays on a chip. In this article, we formulate the placement problem of digital microfluidic biochips with a tree-based topological representation, called T-tree. To the best knowledge of the authors, this is the first work that adopts a topological representation to solve the placement problem of digital microfluidic biochips. We also consider the defect tolerant issue to avoid to use defective cells due to fabrication. Experimental results demonstrate that our approach is more efficient and effective than the previous unified synthesis and placement framework.
TL;DR: This work proposes a design automation method for pin-constrained biochips that manipulate nanoliter volumes of discrete droplets on a microfluidic array that relies on a droplet-trace-based array partitioning scheme and an efficient pin assignment technique, referred to as the “Connect-5 algorithm.”
Abstract: Microfluidics-based biochips, also referred to as lab-on-a-chip, are devices that integrate fluid-handling functions such as sample preparation, analysis, separation, and detection. This emerging technology combines electronics with biology to open new application areas such as point-of-care diagnosis, on-chip DNA analysis, and automated drug discovery. We propose a design automation method for pin-constrained biochips that manipulate nanoliter volumes of discrete droplets on a microfluidic array. In contrast to the direct-addressing scheme that has been studied thus far in the literature, we assign a small number of independent control pins to a large number of electrodes in the biochip, thereby reducing design complexity and product cost. The design procedure relies on a droplet-trace-based array partitioning scheme and an efficient pin assignment technique, referred to as the “Connect-5 algorithm.” The proposed method is evaluated using a set of multiplexed bioassays.
TL;DR: This work analyzes the behavior of quantum-dot cellular automata building blocks in the presence of random cell displacements and finds displacement tolerances to be a function of circuit layout and geometry rather than cell size.
Abstract: We analyze the behavior of quantum-dot cellular automata (QCA) building blocks in the presence of random cell displacements. The QCA cells are modeled using the coherence vector description and simulated using QCADesigner. We evaluate various fundamental circuits: the wire, the inverter, the majority gate, and the two-wire crossing approaches: the coplanar crossover and the multilayer crossover. Our results show that different building blocks have different displacement tolerances. The coplanar crossover and inverter perform the weakest. The wire is the most robust. We have found displacement tolerances to be a function of circuit layout and geometry rather than cell size.
TL;DR: The challenges faced in building crossbar array-based molecular memory are described and a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature is developed.
Abstract: In recent years, many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This article describes the challenges faced in building crossbar array-based molecular memory and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, issues in reading and writing such as memory using CMOS are discussed, and a solution is introduced for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. The proposed memory design is also simulated with consideration to device parameter variations. Thus, the results presented here shed light on important design choices to be made at multiple abstraction levels, from devices to architectures. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.
TL;DR: It is shown that FPGA-based evolvable systems using a virtual reconfigurable circuit are not as sensitive to faults as their area-demanding implementations might suggest.
Abstract: A virtual reconfigurable circuit (VRC) is a domain-specific reconfigurable device developed using an ordinary FPGA in order to easily implement evolvable hardware applications. While a fast partial runtime reconfiguration and application-specific programmable elements represent the main advantages of VRC, the main disadvantage of the VRC is the area consumed. This study describes experiments conducted to estimate how the use of VRC influences the dependability of FPGA-based evolvable systems. It is shown that these systems are not as sensitive to faults as their area-demanding implementations might suggest. An evolutionary algorithm is utilized to design fault tolerant circuits as well as to perform an automatic functional recovery when faults are detected in the configuration memory of the FPGA. All the experiments are performed on models of reconfigurable devices.
TL;DR: An overview of the latest research in the domain of the self-replication of processing elements within a programmable logic substrate, a key prerequisite for achieving system-level fault tolerance in the Embryonics project's bio-inspired approach.
Abstract: The multicellular structure of biological organisms and the interpretation in each of their cells of a chemical program (the DNA string or genome) is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the design of highly robust integrated circuits, endowed with properties usually associated with the living world: self-repair and self-replication. In this article, we provide an overview of our latest research in the domain of the self-replication of processing elements within a programmable logic substrate, a key prerequisite for achieving system-level fault tolerance in our bio-inspired approach.
TL;DR: Maintaining or increasing the dependability of unconventional computational processes is discussed in two different contexts, a bio-inspired computing architecture (the Embryonics project) and a quantum computational architecture ( the QUERIST project).
Abstract: As current microelectronics will reach their physical limits within the foreseeable future, emerging technologies may offer a solution for maintaining the trends to increase computing performance. Biologically-inspired and quantum computing represent two emerging technology vectors for novel computing architectures within nanoelectronics. However, potential benefits will come at the cost of increased device sensitivity to the surrounding environment. This article provides a dependability perspective over these technologies from a designer's standpoint. Maintaining or increasing the dependability of unconventional computational processes is discussed in two different contexts, a bio-inspired computing architecture (the Embryonics project) and a quantum computational architecture (the QUERIST project).
TL;DR: A defect-tolerant SIMD architecture that self-organizes a large number of limited capability nodes with high defect rates into SIMD processing elements to exploit the full potential of future increased device densities is explored.
Abstract: The continual decrease in transistor size (through either scaled CMOS or emerging nanotechnologies) promises to usher in an era of tera to peta-scale integration but with increasing defects. Regardless of fabrication methodology (top-down or bottom-up), defect-tolerant architectures are necessary to exploit the full potential of future increased device densities.This article explores a defect-tolerant SIMD architecture (SOSA) that self-organizes a large number of limited capability nodes with high defect rates into SIMD processing elements. Simulation results show that SOSA matches or exceeds the performance of conventional systems for moderate to large problems, but with lower power density.
TL;DR: A nanoscale reconfigurable mesh which is interconnected by ferromagnetic spin-wave buses which is capable of simultaneously transmitting N waves on each of the spin- wave buses, and three fast labeling algorithms are presented.
Abstract: In this article, we present a nanoscale reconfigurable mesh which is interconnected by ferromagnetic spin-wave buses. In this architecture, unlike the traditional spin-based nano structures which transmit charge, waves are transmitted. As a result, the power consumption of the proposed modules can be low. This reconfigurable mesh, while requiring the same number of switches and buses as the standard reconfigurable mesh, is capable of simultaneously transmitting N waves on each of the spin-wave buses. Because of this highly parallel feature, very fast and fault-tolerant algorithms can be designed. To illustrate the superior performance of the proposed spin-wave reconfigurable mesh, we present three fast labeling algorithms.
TL;DR: This work proposes a hybrid FPGA that uses nanoscale clusters with a functionality similar to the clusters of traditional CMOS FPGAs, and develops models for area and delay of clusters and interconnects of the proposed hybridFPGA.
Abstract: Advances in fabrication technology of nanoscale devices such as nanowires, carbon nanotubes and molecular switches provide new opportunities for implementing cluster-based FPGAs. Extensive research is needed to evaluate area and performance of FPGAs made from these devices and compare with their CMOS counterparts. In this work, we propose a hybrid FPGA that uses nanoscale clusters with a functionality similar to the clusters of traditional CMOS FPGAs. The proposed cluster is constructed by a crossbar of nanowires and can be configured to implement the required LUTs and intracluster MUXes. A CMOS interface is also proposed to provide configuration and memory elements for the nanoscale cluster. In the proposed architecture, inter-cluster routing remains at CMOS scale. We have developed models for area and delay of clusters and interconnects of the proposed hybrid FPGA. FPGA tools are configured with these models and used to synthesize and configure the benchmark circuits onto the hybrid FPGAs with NiSi nanowires or nanotubes. Experiments are conducted to evaluate and compare area and performance of the hybrid FPGA and traditional CMOS FPGA (scaled to 22nm). Up to 82p area reduction was obtained from implementing MCNC benchmarks on the hybrid FPGA. Performance of the hybrid FPGA is shown to be close to that of CMOS FPGA.
TL;DR: This special issue of the ACM Journal on Emerging Technologies in Computing is presented, which consists of a set of papers from the 2006 ACM Computing Frontiers Conference plus a particularly novel paper from the2006 Symposium on Architectural Support for Programming Languages and Operating Systems.
Abstract: I am pleased to present you with this special issue of the ACM Journal on Emerging Technologies in Computing, which consists of a set of papers from the 2006 ACM Computing Frontiers Conference (CF’06) plus a particularly novel paper from the 2006 Symposium on Architectural Support for Programming Languages and Operating Systems. The unifying theme is Reliable Computing, but individual topics range from a magnetic bus technology to aspects of selfhealing, self-configuring, and self-replicating systems. The first article, The Spin-wave Nano-Scale Reconfigurable Mesh and the Labeling Problem by Eshaghian-Wilner, Khitun, Navab, and Wang presents spin-wave buses composing a highly parallel, nanoscale, reconfigurable communication mesh. The high degree of parallelism combined with reconfigurability makes the technology well suited for implementing fault-tolerant communication algorithms. The next set of articles come from a special session at CF’06 on Reliable Computing. This session looked at novel ways of using nature to help us cope with our growing complexity and also help with fault tolerance. The article Design for Dependability in Emerging Technologies by Prodan, Udrescu, Boncalo, and Vladutiu provides an overview of the technologies explicated in the session, and thus serves as a nice introduction to the range of approaches taken by researchers in this global community. Evolving Dependability by Tyrrell and Greensted takes a high-level view of the dependability problem, elucidating how bio-inspired systems embody phylogeny (evolution), ontogeny (reproduction), and epigenesis (adaptation through learning and responding to change). The FPGA systems explored focus on exploiting ontogenetic and phylogenetic processes. The next article, Evolutionary Functional Recovery in Virtual Reconfigurable Circuits by Sekanina addresses reconfigurability for reliability at the circuit level, exploiting phylogenetic processes. Finally, Self-Replication for Reliability: Bio-Inspired Hardware and the Embryonics Project by Tempesti, Mange, Mudry, Rossier, and Stauffer describes an FPGAbased system that exploits ontogenesis, self-generating a system through replication. The final article, A Self-Organizing Defect Tolerant SIMD Architecture by Patwardhan, Dwyer, and Lebeck describes a system targeted for nanotechnologies or CMOS processes with extremely small feature sizes where the underlying substrate will inevitably contain many defects for which we must compensate at the circuit or architectural levels (or both). The architecture described is a system that self-organizes a large number of limited capability nodes.
TL;DR: This article presents a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE, and shows that unlike conventional MOSFET, nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and cylindrical gate geometry.
Abstract: With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this article, we present a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasi-analytical model is effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide insight into how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit. We further show that unlike conventional MOSFET, nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and cylindrical gate geometry.
TL;DR: This special issue of the ACM Journal of Emerging Technologies in Computing Systems is based on papers presented at the 2006 IEEE/ACM Design Automation Conference (DAC), and provides insights on how the parasitic fringe capacitance in CNFET geometries impacts the overall performance of C NFET circuits.
Abstract: This special issue of the ACM Journal of Emerging Technologies in Computing Systems is based on papers presented at the 2006 IEEE/ACM Design Automation Conference (DAC). DAC has recently expanded its focus to include emerging technologies for computing and sensing systems. This broadened focus has been motivated in part by the roadblocks that loom ahead for the continued scaling of Silicon CMOS technology. New materials, new device geometries, and further downscaling of device dimensions and supply voltages are together leading to a significant escalation in manufacturing cost as well as unpredictable circuit performance due to process variability. As a result, experts are predicting that CMOS scaling will stop in the near future, perhaps as early as 2015. Alternative computing technologies being explored today include carbon nan-otubes, nanowires, molecular transistors, spin-based and single-electron devices , DNA-based devices, and hybrid circuits made from mainstream CMOS and newer nanodevices. Together with advances in manufacturing techniques, new design paradigms based on these emerging technologies are being explored. Research groups worldwide are addressing various aspects of circuit and system design such as modeling, analysis, defect tolerance, and synthesis. Another motivation for expanding DAC's focus lies in the recent emergence of electronic systems that integrate MEMS and electrochemical components in sensor systems, biochips, and lab-on-chip devices. Technologies such as mi-crofluidics are now mature enough to allow system integration and system-level design. A call for papers for the JETC special issue was announced soon after DAC 2006. Full-length journal paper submissions were solicited from authors of papers on emerging technology topics at DAC 2006. All submissions went through the regular review process of JETC. After review and appropriate revisions, four papers were accepted for the special issue. In the first article of this special issue, Paul et al. provide a device model for ballistic carbon nanotube FETs (CNFETs). The authors provide insights on how the parasitic fringe capacitance in CNFET geometries impacts the overall performance of CNFET circuits. In the second article, Yuh et al. describe a module-placement technique for defect-tolerant microfluidic biochips. A tree-based topological representation is used to model the placement problem. Next, Xu et al. address a design problem that is especially relevant for low-cost disposable biochips. The authors describe how a small number of input pins can be used to control a larger number of electrodes in a microfluidic array for high-throughput bioassays. In the final article of this special issue, Rad and …