Showing papers in "ACM Journal on Emerging Technologies in Computing Systems in 2008"

High-level synthesis of digital microfluidic biochips

Abstract: Microfluidic biochips offer a promising platform for massively parallel DNA analysis, automated drug discovery, and real-time biomolecular recognition. Current techniques for full-custom design of droplet-based “digital” biochips do not scale well for concurrent assays and for next-generation system-on-chip (SOC) designs that are expected to include microfluidic components. We propose a system design methodology that attempts to apply classical high-level synthesis techniques to the design of digital microfluidic biochips. We focus here on the problem of scheduling bioassay functions under resource constraints. We first develop an optimal scheduling strategy based on integer linear programming. However, because the scheduling problem is NP-complete, we also develop two heuristic techniques that scale well for large problem instances. A clinical diagnostic procedure, namely multiplexed in-vitro diagnostics on human physiological fluids, is first used to illustrate and evaluate the proposed method. Next, the synthesis approach is applied to a protein assay, which serves as a more complex bioassay application. The proposed synthesis approach is expected to reduce human effort and design cycle time, and it will facilitate the integration of microfluidic components with microelectronic components in next-generation SOCs.

Design considerations of sub-mW indoor light energy harvesting for wireless sensor systems

Abstract: For most wireless sensor networks, one common and major bottleneck is the limited battery lifetime. The frequent maintenance efforts associated with battery replacement significantly increase the system operational and logistics cost. Unnoticed power failures on nodes will degrade the system reliability and may lead to system failure. In building management applications, to solve this problem, small energy sources such as indoor light energy are promising to provide long-term power to these distributed wireless sensor nodes. This article provides comprehensive design considerations for an indoor light energy harvesting system for building management applications. Photovoltaic cells characteristics, energy storage units, power management circuit design, and power consumption pattern of the target mote are presented. Maximum power point tracking circuits are proposed which significantly increase the power obtained from the solar cells. The novel fast charge circuit reduces the charging time. A prototype was then successfully built and tested in various indoor light conditions to discover the practical issues of the design. The evaluation results show that the proposed prototype increases the power harvested from the PV cells by 30p and also accelerates the charging rate by 34p in a typical indoor lighting condition. By entirely eliminating the rechargeable battery as energy storage, the proposed system would expect an operational lifetime 10--20 years instead of the current less than 6 months battery lifetime.

Reversible logic synthesis with Fredkin and Peres gates

Abstract: Reversible logic has applications in low-power computing and quantum computing. Most reversible logic synthesis methods are tied to particular gate types, and cannot synthesize large functions. This article extends RMRLS, a reversible logic synthesis tool, to include additional gate types. While classic RMRLS can synthesize functions using NOT, CNOT, and n-bit Toffoli gates, our work details the inclusion of n-bit Fredkin and Peres gates. We find that these additional gates reduce the average gate count for three-variable functions from 6.10 to 4.56, and improve the synthesis results of many larger functions, both in terms of gate count and quantum cost.

Synthesis of reversible sequential elements

Abstract: To construct a reversible sequential circuit, reversible sequential elements are required. This work presents novel designs of reversible sequential elements such as the D latch, JK latch, and T latch. Based on these reversible latches, we construct the designs of the corresponding flip-flops. Then we further discuss the physical implementations of our designs based on electron waveguide Y-branch switch technology. Test costs, including test generation and test application, of reversible sequential circuits with these reversible flip-flops are also discussed. Compared with previous work, the implementation cost of our new designs, including the number of gates and the number of garbage outputs, is significantly reduced. The number of gates in our designs is 47.4p of the designs in previous work on average. The number of garbage outputs in our designs is 25p of the designs in previous work on average.

Arithmetic on a distributed-memory quantum multicomputer

Abstract: We evaluate the performance of quantum arithmetic algorithms run on a distributed quantum computer (a quantum multicomputer). We vary the node capacity and I/O capabilities, and the network topology. The tradeoff of choosing between gates executed remotely, through “teleported gates” on entangled pairs of qubits (telegate), versus exchanging the relevant qubits via quantum teleportation, then executing the algorithm using local gates (teledata), is examined. We show that the teledata approach performs better, and that carry-ripple adders perform well when the teleportation block is decomposed so that the key quantum operations can be parallelized. A node size of only a few logical qubits performs adequately provided that the nodes have two transceiver qubits. A linear network topology performs acceptably for a broad range of system sizes and performance parameters. We therefore recommend pursuing small, high-I/O bandwidth nodes and a simple network. Such a machine will run Shor's algorithm for factoring large numbers efficiently.

Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips

Abstract: Microfluidic biochips are revolutionizing high-throughput DNA sequencing, immunoassays, and clinical diagnostics. As high-throughput bioassays are mapped to digital microfluidic platforms, the need for design automation techniques is being increasingly felt. Moreover, as most applications of biochips are safety-critical in nature, defect tolerance is an essential system attribute. Several synthesis tools have recently been proposed for the automated design of biochips from the specifications of laboratory protocols. However, only a few of these tools address the problem of defect tolerance. In addition, most of these methods do not consider the problem of droplet routing in microfluidic arrays. These methods typically rely on postsynthesis droplet routing to implement biochemical protocols. Such an approach is not only time consuming, but also imposes an undue burden on the chip user. Postsynthesis droplet routing does not guarantee that feasible droplet pathways can be found for area-constrained biochip layouts; nonroutable fabricated biochips must be discarded. We present a synthesis tool that integrates defect tolerance and droplet routing in the design flow. Droplet routability, defined as the ease with which droplet pathways can be determined, is estimated and integrated in the synthesis procedure. Presynthesis and postsynthesis defect-tolerance methods are also presented. We use a large-scale protein assay as a case study to evaluate the proposed synthesis method.

Parametric yield management for 3D ICs: Models and strategies for improvement

Abstract: Three-Dimensional (3D) Integrated Circuits (ICs) that integrate die with Through-Silicon Vias (TSVs) promise to continue system and functionality scaling beyond the traditional geometric 2D device scaling. 3D integration also improves the performance of ICs by reducing the communication time between different chip components through the use of short TSV-based vertical wires. This reduction is particularly attractive in processors where it is desirable to reduce the access time between the main logic die and the L2 cache or the main memory die. Process variations in 2D ICs lead to a drop in parametric yield (as measured by speed, leakage and sales profits), which forces manufacturers to speed bin their chips and to sell slow chips at reduced prices. In this paper we develop a model to quantify the impact of process variations on the parametric yield of 3D ICs, and then we propose a number of integration strategies that use a graph-theoretic framework to maximize the performance, parametric yield and profits of 3D ICs. Comparing our proposed strategies to current yield-oblivious methods, it is demonstrated that it is possible to increase the number of 3D ICs in the fastest speed bins by almost 2×, while simultaneously reducing the number of slow ICs by 29.4p. This leads to an improvement in performance by up to 6.45p and an increase of about 12.48p in total sales revenue using up-to-date market price models.

PicoServer: Using 3D stacking technology to build energy efficient servers

Abstract: This article extends our prior work to show that a straightforward use of 3D stacking technology enables the design of compact energy-efficient servers. Our proposed architecture, called PicoServer, employs 3D technology to bond one die containing several simple, slow processing cores to multiple memory dies sufficient for a primary memory. The multiple memory dies are composed of DRAM. This use of 3D stacks readily facilitates wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency means that thermal constraints, a concern with 3D stacking, are easily satisfied. We extend our original analysis on PicoServer to include: (1) a wider set of server workloads, (2) the impact of multithreading, and (3) the on-chip DRAM architecture and system memory usage. PicoServer is intentionally simple, requiring only the simplest form of 3D technology where die are stacked on top of one another. Our intent is to minimize risk of introducing a new technology (3D) to implement a class of low-cost, low-power compact server architectures.

An energy management framework for energy harvesting embedded systems

Abstract: Energy harvesting (also known as energy scavenging) is the process of generating electrical energy from environmental energy sources. There exists a variety of different energy sources such as solar energy, kinetic energy, or thermal energy. In recent years, this term has been frequently applied in the context of small autonomous devices such as wireless sensor nodes. In this article, a framework for energy management in energy harvesting embedded systems is presented. As a possible scenario, we focus on wireless sensor nodes that are powered by solar cells. We demonstrate that classical power management solutions have to be reconceived and/or new problems arise if perpetual operation of the system is required. In particular, we provide a set of algorithms and methods for various application scenarios, including real-time scheduling, application rate control, as well as reward maximization. The goal is to optimize the performance of the application subject to given energy constraints. Our methods optimize the system performance which, for example, allows the usage of smaller solar cells and smaller batteries. Furthermore, we show how to dimension important system parameters like the minimum battery capacity or a sufficient prediction horizon. Our theoretical results are supported by simulations using long-term measurements of solar energy in an outdoor environment. In contrast to previous works, we present a formal framework which is able to capture the performance, the parameters, and the energy model of various energy harvesting systems. We combine different viewpoints, include corresponding simulation results, and provide a thorough discussion of implementation aspects.

Molecular QCA design with chemically reasonable constraints

Abstract: In this article we examine the impacts of the fundamental constraints required for circuits and systems made from molecular Quantum-dot Cellular Automata (QCA) devices. Our design constraints are “chemically reasonable” in that we consider the characteristics and dimensions of devices and scaffoldings that have actually been fabricated. This work is a necessary first step for any work in QCA CAD, and can also help shape experiments in the physical sciences for emerging, nano-scale devices. Our work shows that QCA circuits, scaffoldings, substrates, and devices should all be considered simultaneously. Otherwise, there is a very real possibility that the devices and scaffoldings that are eventually manufactured will result in devices that only work in isolation. “Chemically reasonable” also means that expected manufacturing defects must be considered. In our simulations we introduce defects associated with self-assembled systems into various designs to begin to define manufacturing tolerances. This work is especially timely as experimentalists are beginning to work on merging experimental tracks that address devices and scaffolds—and the end result should facilitate correct logical operations.

Multilayer stacking technology using wafer-to-wafer stacked method

Abstract: We have developed a new three-dimensional stacking technology using the wafer-to-wafer stacked method Electrical conductivity between each wafer is almost 100p and contact resistance is less than 07Ω between a through-silicon via (TSV) and a microbump We have also created a prototype of a three-layer stacking device using our technology, where each wafer for the stacking is fabricated by using 018um CMOS technology based on 8-inch wafers The device is operated by two times the frequency of the multichip module (MCM) device case using a two-dimensional device with identical functions and minimally different power consumption The yields obtained from the results comprising all functional tests are over 60p

A model for computing and energy dissipation of molecular QCA devices and circuits

Abstract: Quantum-dot Cellular Automata is an emerging technology that offers significant improvements over CMOS. Recently QCA has been advocated as a technology for implementing reversible computing. However, existing tools for QCA design and evaluation have limited capabilities. This paper presents a new mechanical-based model for computing in QCA. By avoiding a full quantum-thermodynamical calculation, it offers a classical view of the principles of QCA operation and can be used in evaluating energy dissipation for reversible computing. The proposed model is mechanically based and is applicable to six-dot (neutrally charged) QCA cells for molecular implementation. The mechanical model consists of a sleeve of changing shape; four electrically charged balls are connected by a stick that rotates around an axle in the sleeve. The sleeve acts as a clocking unit, while the angular position of the stick within the changing shape of the sleeve, identifies the phase for quasi-adiabatic switching. A thermodynamic analysis of the proposed model is presented. The behaviors of various QCA basic devices and circuits are analyzed using the proposed model. It is shown that the proposed model is capable of evaluating the energy consumption for reversible computing at device and circuit levels for molecular QCA implementation. As applicable to QCA, two clocking schemes are also analyzed for energy dissipation and performance (in terms of number of clocking zones).

Reliability analysis for flexible electronics: Case study of integrated a-Si:H TFT scan driver

Abstract: Flexible electronics fabricated on thin-film, lightweight, and bendable substrates (e.g., plastic) have great potential for novel applications in consumer electronics such as flexible displays, e-paper, and smart labels; however, the key elements, namely thin-film transistors (TFTs), for implementing flexible circuits often suffer from electrical instability. Therefore, thorough reliability analysis is critical for flexible circuit design to ensure that the circuit will operate reliably throughout its lifetime. In this article we propose a methodology for reliability simulation of hydrogenated amorphous silicon (a-Si:H) TFT circuits. We show that: (1) the threshold voltage (VTH) shift of a single TFT can be estimated by analyzing its operating conditions; and (2) the circuit lifetime can be predicted accordingly by using SPICE-like simulators with proper modeling. We also propose an algorithm to reduce the simulation time by orders of magnitude, with good prediction accuracy. To validate our analytical model and simulation methodology, we compare simulation results with the actual circuit measurements of an integrated a-Si:H TFT scan driver fabricated on a glass substrate and we demonstrate very good consistency.

Carbon nanotube transistor compact model for circuit design and performance optimization

Abstract: In this paper, we describe the development of the Stanford University Carbon Nanotube FET (CNFET) Compact Model. The CNFET Model is a circuit-compatible, compact model which describes enhancement-mode, CMOS-like CNFETs. It can be used to simulate both functionality and performance of large-scale circuits with hundreds of CNFETs. To produce realistic and relevant results, the model accounts for several practical non-idealities such as scattering in the near-ballistic channel, effects of the source/drain extension region, and charge-screening for multiple-nanotube CNFETs. The model also includes a full transcapacitance network for more accurate transient and AC results. The Stanford University CNFET Model is implemented in both HSPICE macro language and VerilogA. The VerilogA implementation shows speedups of roughly 7x∼15x over HSPICE. Applications of the model suggest that n- and p-CNFETs will have 6x and 13x speed advantage over Si n- and p-MOSFETs respectively at the 32nm node, and that a CNT density of 250 CNTs/um is ideal for multiple-nanotube gates. Such a compact CNFET model will be absolutely essential in ushering in the Design Era of CNFET circuits as carbon nanotube technology outgrows its “science discovery” phase.

High-level interconnect model for the quantum logic array architecture

Abstract: We summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportation-based logical interconnect. The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution over large distances. The QLA's logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a 2048-bit number using Shor's quantum factoring algorithm. Our physical-level assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing.

Investigating the effects of fine-grain three-dimensional integration on microarchitecture design

Abstract: In this article we propose techniques that enable efficient exploration of the 3D design space, where each logical block can span more than one silicon layer. Fine-grain 3D integration provides reduced intrablock wire delay as well as improved power consumption. However, the corresponding power and performance advantage is usually underutilized, since various implementations of multilayer blocks require novel physical design and microarchitecture infrastructure to explore 3D microarchitecture design space. We develop a cubic packing engine which can simultaneously optimize physical and architectural design for efficient vertical integration. This technique selects the individual unit designs from a set of single-layer or multilayer implementations to get the best microarchitectural design in terms of performance, temperature, or both. Our experimental results using a design driver of a high-performance superscalar processor show a 36p performance improvement over traditional 2D for 2--4 layers and 14p over 3D with single-layer unit implementations. Since thermal characteristics of 3D integrated circuits are among the main challenges, thermal-aware floorplanning and thermal via insertion techniques are employed to keep the peak temperatures below threshold.

ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management

Abstract: Power dissipation is a major bottleneck for emerging applications, such as implantable systems, digital cameras, and multimedia processors. Each of these applications is essentially designed as an Analog/Mixed-Signal System-on-a-Chip (AMS-SoC). These AMS-SoCs are typically operated from a single power-supply source which is a battery providing a constant supply voltage. In order to reduce power dissipation of the AMS-SoCs, multiple-supply voltage and/or variable-supply voltage is used as an attractive low-power design approach. In the multiple-/variable-supply voltage AMS-SoCs the use of a DC-to-DC voltage-level shifter is critical. The voltage-level shifter is an overhead when its own power dissipation is high. In this article a new DC-to-DC voltage-level shifter is introduced that performs level-up shifting, level-down shifting, and blocking of voltages and is called Universal Level Shifter (ULS). The ULS is a unique component that reduces dynamic power and leakage of the AMS-SoCs while facilitating their reconfigurability. The system-level architectures for three AMS-SoCs, such as Drug Delivery Nano-Electro-Mechanical-System (DDNEMS), Secure Digital Camera (SDC), and Net-centric Multimedia Processor (NMP) are introduced to demonstrate the use the ULS for system-level power management. The article presents a design flow and an algorithm for optimal design of the ULS using a dual-Vth high-κ technique for efficient realization of ULS. A prototype ULS is presented for 32nm nano-CMOS technology node. The robustness of the ULS design is examined by performing three types of analysis, such as parametric, load, and power. It is observed that the ULS produces a stable output for voltages as low as 0.35 V and loads varying from 50 fF to 120 fF. The average power dissipation of the ULS with a 82 fF capacitive load is 5 μ W.

Scaling self-timed systems powered by mechanical vibration energy harvesting

Abstract: Passive energy harvesting from mechanical vibration has wide application in wearable devices and wireless sensors to complement or replace batteries. Energy harvesting efficiency can be increased by eliminating AC/DC conversion. A test chip demonstrating self-timing, power-on reset circuitry, and dynamic memory for energy harvesting AC voltages has been designed in 180 nm CMOS and tested. An energy scalable DSP architecture implements FIR filters that consume as little as 170 pJ per output sample. The on-chip DRAM retains data for up to 28 ms while register data is retained down to a supply voltage of 153 mV. Circuit operation is confirmed for supply frequencies between 60 Hz and 1 kHz with power consumption below 130 μW. Reaching the limits of miniaturization will require approaching the limits of power dissipation. We extrapolate from this DSP architecture to find the minimum volume required for mechanical vibration energy harvesting sensors.

Routing in self-organizing nano-scale irregular networks

Abstract: The integration of novel nanotechnologies onto silicon platforms is likely to increase fabrication defects compared with traditional CMOS technologies. Furthermore, the number of nodes connected with these networks makes acquiring a global defect map impractical. As a result, on-chip networks will provide defect tolerance by self-organizing into irregular topologies. In this scenario, simple static routing algorithms based on regular physical topologies, such as meshes, will be inadequate. Additionally, previous routing approaches for irregular networks assume abundant resources and do not apply to this domain of resource-constrained self-organizing nano-scale networks. Consequently, routing algorithms that work in irregular networks with limited resources are needed.In this article, we explore routing for self-organizing nano-scale irregular networks in the context of a Self-Organizing SIMD Architecture (SOSA). Our approach trades configuration time and a small amount of storage for reduced communication latency. We augment an Euler path-based routing technique for trees to generate static shortest paths between certain pairs of nodes while remaining deadlock free. Simulations of several applications executing on SOSA show our proposed routing algorithm can reduce execution time by 8% to 30%.

FinFET-based power simulator for interconnection networks

Abstract: Double-gate FETs, specifically FinFETs, are emerging as promising substitutes for bulk CMOS at the 32nm technology node and beyond because of the various obstacles to scaling faced by CMOS, such as short-channel effects, leakage power, and process variations. Another trend in chip multiprocessor design is incorporation of sophisticated on-chip interconnection networks. However, such networks are significant power-consumers. In this article, we address these two trends by presenting a power simulator for FinFET-based on-chip interconnection networks. It estimates both dynamic and leakage power. We present results for various FinFET design styles and temperatures (since leakage power changes drastically with temperature), and show that one FinFET design style may be much superior to another from the power consumption point of view.

A meshless, spectrally accurate, integral equation solver for molecular surface electrostatics

Abstract: The need to determine electrostatic fields in domains bounded by molecular surfaces arises in a number of nanotechnology applications including: biomolecule design, carbon nanotube simulation, and molecular electron transport analysis. Molecular surfaces are typically smooth, without the corners common in electrical interconnect problems, but are often so geometrically complicated that numerical evaluation of the associated electrostatic fields is extremely time-consuming. In this paper we describe and demonstrate a meshless spectrally-accurate integral equation method that only requires a description of the molecular surface in the form of a collection of surface points. Our meshless method is a synthesis of techniques, suitably adapted, including: spherical harmonic surface interpolation, spectral-element-like integral equation discretization, integral desingularization via variable transformation, and matrix-implicit iterative matrix solution. The spectral accuracy of this combined method is verified using analytically solvable sphere and ellipsoid problems, and then its accuracy and efficiency is demonstrated numerically by solving capacitance and coupled Poisson/linearized Poisson-Boltzmann problems associated with a commonly used model of a molecule in solution. The results demonstrate that for a tolerance of 10−3 this new approach reduces the number of unknowns by as much as two orders of magnitude over the more commonly used flat panel methods.

High parallelism, portability, and broad accessibility: Technologies for genomics

Abstract: Biotechnology is an area of great innovations that promises to have deep impact on everyday life thanks to profound changes in biology, medicine, and health care. This article will span from the description of the biochemical principles of molecular biology to the definition of the physics that supports the technology and to the devices and algorithms necessary to observe molecular events in a controlled, portable, and highly parallel manner. Throughout this discussion, constant attention will be given to the ultimate goals and applications of these innovations as well as to the related issues.

Formal methods for the analysis and synthesis of nanometer-scale cellular arrays

Abstract: Nanometer-scale structures suitable for computing have been investigated by several research groups in recent years. A common feature of these structures is their dynamic evolution through cascaded local interactions embedded on a discrete grid. Finding configurations capable of conducting computations is a task that often requires tedious experiments in laboratories. Formal methods—though used extensively for the specification and verification of software and hardware computing systems—are virtually unexplored with respect to computational structures at atomic scales. This paper presents a systematic approach toward the application of formal methods in this context, using techniques like abstraction, model-checking, and symbolic representations of states to explore and discover computational structures. The proposed techniques are applied to a system of CO molecules on a grid of Copper atoms, resulting in the design of a complete library of combinational logic gates based on this molecular system. The techniques are also applied on (more general) systems of cellular automata that employ an asynchronous mode of timing. The use of formal methods may narrow the gap between Physical Chemistry and Computer Science, allowing the description of interactions of nanometer scale systems on a level of abstraction suitable to devise computing devices.

Automated module assignment in stacked-Vdd designs for high-efficiency power delivery

Abstract: With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a critical issue in today's VLSI designs, especially for 3D IC technologies. To alleviate the pin limitation problem, a stacked-Vdd circuit paradigm has recently been proposed in the literature. However, for a circuit designed using this paradigm, a significant amount of power may be wasted if modules are not carefully assigned to different Vdd domains. In this article, we present a partition-based algorithm for efficiently assigning modules at the floorplanning level, so as to reuse currents between Vdd domains and minimize the power wasted during the operation of the circuit. Experimental results on both 3D and 2D ICs show that compared with assigning modules to different Vdd domains using enumeration and simulated annealing, our algorithm can generate circuits with competitive power and IR noise performance, while being orders of magnitude faster.

Introduction to design techniques for energy harvesting

Abstract: There is a growing interest in emerging energy harvesting methods, which have become more realistic in recent years. Thus, energy scavenging approaches are now considered real contenders as an alternative for powering ubiquitously deployed mobile and wireless electronic devices such as sensor network nodes. Low-power and energy-efficient circuits and systems have always attracted attention, however, there is a significant increase in demand for their usage and research to improve them in recent years. This demand is driven by several factors such as increasing energy costs for medium-to-large systems and the lack of sufficient battery power for ever increasing functionality of small and mobile devices. Further, mobility makes energy harvesting even more crucial. This special issue reports the recent advances in the emerging energy harvesting area as well as in energy-efficient circuits and systems. In the first article, by Wenck et al., the authors propose techniques to exploit the AC nature of mechanical vibration energy harvesting to increase efficiency and decrease cost. The techniques cover self-times circuits for maintaining the timing constrainst in wide voltage variations; fast power-on-reset circuits to initialize DSP pipelines; and dynamic memories to keep state information across supply cycles. The article by Wang et al. discusses design considerations of sub-mw indoor light energy harvesting for wireless sensor systems. A photovoltaic-panelbased energy harvesting is chosen for the wireless sensor system design. The authors employ a maximum power point tracking scheme to improve the power

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs

Abstract: This article presents a holistic hybrid design methodology for low-power, low-cost, testable digital designs using low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs). An alternate scaling rule under low thermal budget (due to flexible substrate) is developed to improve the performance of TFTs in the presence of process variation. We demonstrate that LTPS TFTs can be further optimized for ultralow-power subthreshold operation with performances comparable to contemporary single-crystal silicon-on-insulator (c-Si SOI) devices after process optimization. The optimized LTPS TFTs with high current drivability and less variability can comprise a promising low-cost option to augment Si CMOS technology, opening up a plethora of new hybrid 3D applications. We illustrate one such application: IC testing. Testing of complex VLSI systems is a prime concern due to design cost of DFT circuits, area/delay overheads, and poor test confidence. To harness the benefits of TFT technology, a novel low-power, process-tolerant, generic, and reconfigurable test structure designed using LTPS TFTs is proposed to reduce the test cost, as well as to improve diagnosability and verifiability, of complex VLSI systems. Due to proper optimization of TFT devices, the proposed test structure consumes low power but operates with reasonable performance. Furthermore, the test circuits do not consume any silicon area because they can be integrated on-chip using 3D technology. Since the test architecture is reconfigurable, this eliminates the need to redesign built-in-self-test (BIST) components that may vary from one processor generation to another. We have developed test structures using 200nm TFT devices and evaluated them on designs implemented in 130nm bulk CMOS. For circuit simulations, we have developed a SPICE-compatible model for TFT devices. The BIST components designed using the test structures operate at 0.8--4.3 GHz (compared to 8.2 GHz in bulk CMOS) with low power consumption. The enhanced scan cells partially implemented in TFT (3D hybrid design) consume ∼24p less power and ∼15--20p less area of Si die compared to conventional bulk-Si design (2D planar design), with minimal delay overhead.

SCT: A novel approach for testing and configuring nanoscale devices

Abstract: Novel strategies are necessary to efficiently test and configure emerging reconfigurable nanoscale devices, in addition to providing defect tolerance. This is mainly due to the high defect densities that are expected for these devices. Among different approaches, reconfiguration-based defect avoidance has proven to be a practical solution. However, configuration time, test time, and defect-map size remain among the major challenges for these new devices. In this article, we propose a new approach (called SCT) that simultaneously performs test and configuration. The proposed method uses a built-in self-test (BIST) scheme for test and defect tolerance. The method is based on testing reconfigurable nanoblocks at the time of implementing a function of a desired application on that block. The SCT method considerably reduces the total test and configuration time. It also eliminates the need for storing the location of defects in a defect map on- or off-chip. The presented probabilistic analysis results show the effectiveness of this method in terms of test and configuration time for architectures with rich interconnect resources. Also, a Verilog simulation model is developed for crossbar-based nano-architectures. This model is used to implement several MCNC benchmarks based on the proposed SCT method. The simulation results demonstrate efficiency of the method in terms of test time and yield under different defect rates.