Showing papers in "ACM Journal on Emerging Technologies in Computing Systems in 2010"

Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs

Abstract: Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.

Reversible circuit synthesis using a cycle-based approach

Abstract: Reversible logic has applications in various research areas, including signal processing, cryptography and quantum computation. In this article, direct NCT-based synthesis of a given k-cycle in a cycle-based synthesis scenario is examined. To this end, a set of seven building blocks is proposed that reveals the potential of direct synthesis of a given permutation to reduce both quantum cost and average runtime. To synthesize a given large cycle, we propose a decomposition algorithm to extract the suggested building blocks from the input specification. Then, a synthesis method is introduced that uses the building blocks and the decomposition algorithm. Finally, a hybrid synthesis framework is suggested that uses the proposed cycle-based synthesis method in conjunction with one of the recent NCT-based synthesis approaches which is based on Reed-Muller (RM) spectra.The time complexity and the effectiveness of the proposed synthesis approach are analyzed in detail. Our analyses show that the proposed hybrid framework leads to a better quantum cost in the worst-case scenario compared to the previously presented methods. The proposed framework always converges and typically synthesizes a given specification very fast compared to the available synthesis algorithms. Besides, the quantum costs of benchmark functions are improved about 20p on average (55p in the best case).

Integrated control-path design and error recovery in the synthesis of digital microfluidic lab-on-chip

Abstract: Recent advances in digital microfluidics have led to tremendous interest in miniaturized lab-on-chip devices for biochemical analysis Synthesis tools have also emerged for the automated design of lab-on-chip from the specifications of laboratory protocols However, none of these tools consider control flow or address the problem of recovering from fluidic errors that can occur during on-chip bioassay execution We present a synthesis method that incorporates control paths and an error-recovery mechanism in the design of a digital microfluidic lab-on-chip Based on error-propagation estimates, we determine the best locations for fluidic checkpoints during biochip synthesis A microcontroller coordinates the implementation of the control-flow-based bioassay by intercepting the synthesis results that are mapped to the software programs Real-life bioassay applications are used as case studies to evaluate the proposed design method For a representative protein assay, compared to a baseline chip design, the biochip with a control path can reduce the completion time by 30p when errors occur during the implementation of the bioassay

Gated-diode FinFET DRAMs: Device and circuit design-considerations

Abstract: Scaling bulk CMOS SRAM technology for on-chip caches beyond the 22nm node is questionable, on account of high leakage power consumption, performance degradation, and instability due to process variations. Recently, two-three transistor one gated-diode (2T/3T1D) DRAMs were proposed as alternatives to address the SRAM variability problem, with an emphasis on high-activity embedded cache applications. They are highly competitive to SRAM in terms of performance, while having a smaller power and area footprint at lower technology nodes. The current evolutionary trend in transistor structures is moving toward an era of multigate devices, which makes it necessary to identify design issues and advantages of gated-diode DRAMs implemented in a multigate technology.In this work, we address gated-diode DRAM design in FinFET technology using mixed-mode 2D-device simulations. We revisit the model of internal voltage gain in bulk gated diodes and extend it to provide quantitative insight into designing Fin gated diodes, that is, gated diodes in FinFET technology. To this effect, we propose FinFET variants of the bulk gated-diode configuration and identify parameters that are critical to enhancing the retention time and read current in 2T/3T1D FinFET DRAMs. Additionally, we show the superiority of 2T1D FinFET DRAM over 6T FinFET SRAM having pass-gate feedback (6T PGFB) and 2T1D bulk DRAM under the effect of physical parameter process variations using a quasi--Monte Carlo method implemented in FinE, an environment we have developed for double-gate circuit design that integrates Sentaurus TCAD from Synopsys with the Spice3-UFDG double-gate compact model from University of Florida, under a single framework. Finally, we present a new tunable threshold gated diode FinFET amplifier which uses an n-type gated diode for voltage-boosting, along with a p-type gated diode for zero-suppression.

Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture

Abstract: In order to continue technology scaling beyond CMOS, diverse nanoarchitectures have been proposed in recent years based on emerging nanodevices, such as nanotubes, nanowires, etc. Among them, some hybrid nano/CMOS reconfigurable architectures enjoy the advantage that they can be fabricated using photolithography. NATURE is one such architecture that we have proposed recently. It comprises CMOS reconfigurable logic and CMOS fabrication-compatible nano RAMs. It uses distributed high-density and fast nano RAMs as on-chip storage for storing multiple reconfiguration copies, enabling fine-grain cycle-by-cycle reconfiguration. It supports a highly efficient computational model, called temporal logic folding, which makes possible more than an order of magnitude improvement in logic density and area-delay product, significant power reduction, and significant design flexibility in performing area-delay trade-offs.In this article, we extend NATURE in various dimensions, evaluating various FPGA approaches in the context of today's emerging technologies. First, we explore the introduction of embedded coarse-grain modules in the fine-grain NATURE architecture and present a unified dynamically reconfigurable architecture, which can significantly enhance NATURE's computation power for data-dominated applications. Second, we explore a 3D architecture for NATURE in which the nano RAM for reconfiguration storage is on one layer and the rest of the CMOS logic on another layer. This leads to further improvements in logic density and performance. Finally, we explore the possibility of using FinFETs, an emerging double-gate CMOS technology, to implement NATURE. Since power consumption is an important consideration in the deep nanometer regime, especially for FPGAs, we present a back-gate biasing methodology for flexible threshold voltage adjustment in FinFETs to significantly reduce NATURE's power consumption. Simulation results demonstrate the efficacy of the proposed methods.

An information-theoretic analysis of quantum-dot cellular automata for defect tolerance

Abstract: Quantum-dot cellular automata (QCA) has been advocated as a promising emerging nanotechnology for designing future nanocomputing systems. However, at device level, the large number of expected defects represents a significant hurdle for reliable computation in QCA-based systems. In this paper, we present an information-theoretic approach to investigate the relationship between defect tolerance and redundancy in QCA devices. By modeling defect-prone QCA devices as unreliable information processing media, we determine the information transfer capacity, as bound on the reliability that QCA devices can achieve. The proposed method allows to evaluate the effectiveness of redundancy-based defect tolerance in an effective and quantitative manner.